Test Ideas: Sync sine waves over three decades

The test and calibration of audio-frequency circuits and systems often require a sine wave with an accurate amplitude and frequency and a low total harmonic distortion (THD). Some test applications require that a signal generator have the ability to accurately synchronize the output with an external timing signal.

The synchronizer IC (74HC4046) is a phase-locked loop (PLL) with one voltage-controlled oscillator (VCO) and three phase/frequency detectors. The best phase/frequency detector to use for maintaining a low THD with constant amplitude is one with a frequency-capture range equal to the VCO frequency range (the maximum frequency minus the minimum frequency). In this case, it is the phase-comparator 2 (PHC 2 out) output.

A 74HC4060 general-purpose binary frequency divider generates at its Q6 output the 74HC4046’s VCO output divided by 64. This divided VCO output feeds back to the 74HC4046’s phase/frequency comparator input (Comp In). When the VCO is phase locked, it synchronizes the pulse input (Sig In) to the divided VCO output. Components C1 and R1 set the VCO’s frequency range from the minimum to the maximum level of the VCO’s input-voltage range.

The MAX297 switched-capacitor low-pass filter that follows the PLL has a cutoff frequency (from analog signal input to analog output) equal to 1/50th of the frequency at its clock input. Any signal with a ratio to the clock frequency lower than 50 is heavily attenuated (Ref. 1). That clock signal is, in this case, the VCO output.

The analog input is the same 74HC4060 Q6 output square wave used for the PLL feedback. Because the clock and signal inputs always have a frequency ratio of 64, the fundamental sine wave of the input signal always falls within the filter bandpass, appearing at the output. No other harmonic component of the input square wave will fall within this bandpass, because the ratio of the clock frequency to frequency is always less than 50.

The fact that the filter’s analog input signal is a 50% duty cycle square wave helps in this application because such a square wave contains only odd harmonics of the fundamental. The lowest-frequency harmonic is then the third, which is well within the filter’s deep-attenuation range (frequency to clock ratio is 21.33 for the 3rd harmonic).

You can frequency-modulate the synchronization signal, but that task forces a compromise between the synchronization-tracking speed (or maximum modulation frequency and depth) and the frequency-locking range. The PLL’s low-pass filter components—R2, R3, and C2—set that range. Modulation speed is limited for the values in the figure because those values are optimized for an extended-frequency locking range.