Light on the Road to Low-k Integration

In developing new ultralow-k (ULK) materials, two major concerns continue to plague the industry: the increasing porosity of ULK materials and potential film damage induced during process integration. This article provides an in-depth understanding of both issues, and presents some promising results from an integration scheme based on a metalhard mask and new plasma chemistries. The ULK materials of particular interest are SiOC:H-based organosilicate glasses (OSG).

Porosity matters

It is well known that increased porosity in dielectric films has a detrimental impact on the material's thermo-mechanical properties. Further, as the percentage of porosity is increased, the elastic modulus and thermal conductivity deteriorate more rapidly (power law)¹ than the corresponding decreases in density and k value, which are linear.² However, recent studies have demonstrated such deterioration may be essentially reversed with subsequent curing techniques, including thermal, plasma, UV and electron-beam, successfully enhancing thermo-mechanical properties.

In UV curing, for example, the combined action of UV radiation and the resulting thermal activation rearranges the bonding structure of the SiOC:H matrixin the OSG film, thereby enhancing film stiffness while preserving the hydrophobic nature and pristine porosity of the film.

The rearrangement follows a transition of the large-angle Si-O-Si bonds toward the more stable small-angle or "network" configuration, as well as an increase in the degree of cross-linking. Therefore, to develop an optimal UV cure process, a selective photolysis is required together with a good understanding of the matrix structure's chain mobility.³

Pore coalescence

To achieve more rugged low-k films, a reduction in density without pore aggregation, or coalescence, is highly desirable. However, with increased porosity, the incidence of pore coalescence rises, thus adding to the complexity in new ULK dielectric synthesis.

Pore coalescence can be detrimental on many levels. Unlike small, ordered pores <2.0 nm in diameter, which are shown to have a positive impact on elastic modulus, random coalescing pores are shown to diminish mechanical properties.⁴ Moreover, coalescing pores increase the incidence of larger pore formation, which in turn may impair step coverage in copper barrier scaling. Finally, the degree of pore connectivity, or lack thereof, can provide a pathway for the penetration of gas contaminants, moisture, wet clean chemicals, chemical mechanical planarization (CMP) slurries, and atomic layer deposition (ALD) precursors for barrier deposition, and therefore needs to be controlled and maintained below 2.0 nm micro-connectivity.⁵

Application-specific

In addition to these general considerations, low-k developments are application-specific and, as such, additional requirements may come into play. For logic applications, for instance, an ideal film would be ULK with limited porosity. However, at this point of development, to achieve the desired k value, porosity percentages are necessarily on the rise.

Memory applications follow the logic route with a delay of about five years. In this case, low-k films must be able to withstand higher voltage operations, typically on the order of 15 V, and have high mechanical properties with an elastic modulus exceeding 15 GPa. For specific memory applications such as flash, there may be additional requirements of highthermal stability and high-field time-dependent dielectric breakdown (TDDB), depending on the process flow.

Integration schemes

The integration of copper and low-k films is complicated by the impact on copper resistivity and the effective k value,⁶ where the relative importance of statistical fluctuations of process parameters continues to increase.⁷ Furthermore, the difficulty of defining the right methodology — a methodology that isolates fundamental aspects from imperfect processing, thus enabling a realistic "interconnect" assessment — cannot be overlooked. Each contributes equally to finding the right IC solution for back-end-of-line (BEOL) integration relative to specific starting materials.

Focusing purely on process-induced damage to the low-k film inherent to copper damascene integration, the films are known to be increasingly sensitive to both physical and chemical damage as k values decrease. The damage is manifested as a localized increase of the k-value in integrated structures and/or degradation in reliability that can jeopardize the benefits of using low-k dielectrics.⁸ Process-induced damage to the low-k film predominantly occurs during plasma exposure — etch, ash and post-CMP plasma clean.

Metal hard masks

A clear relationship between specific material properties and the degree of plasma-induced damage is lacking. At IMEC, solutions to mitigate dielectric deterioration from etch and ash plasma exposure are primarily based on tailoring integration schemes, including stack definition, plasma chemistry selection, and etch and ash process sequence.⁹ For low-k films with porosities <10%, a resist mask (RM)-basedintegration scheme is used; for higher-porosity materials, IMEC has shifted to a metal hard mask (MHM)-based integration scheme (Fig. 1).

1. To mitigate the deterioration of ultralow-k films, integration schemes have been proposed, including resist mask (RM), metal hard mask (MHM) for porosity <20%, and MHM for porosity >20%.

However, with this integration strategy, as damage during patterning is minimized, subsequent damage to the dielectric films may occur during CMP¹⁰ and/or plasma-based post-CMP cleaning following copper reduction and during residual particle removal.

In previous studies, researchers demonstrated that the mechanical properties of the dielectric play a major role in post-CMP defect generation.^10,11 They also showed that enhancing the mechanical properties at the surface of the ULK film is a viable route to mitigating CMP-induced mechanical damage. Therefore, prior to MHM deposition, a very thin SiC layer (~5 nm) was deposited to enhance the mechanical properties of the film. Other groups used SiO₂ prior to deposition, which, in more general terms, is called a dielectric protection layer (DPL). Applied to dense and medium porosity low-k films, the MHM scheme has reduced the discrepancy between bulk (as-deposited) k values and integrated (k_eff) values to 0.0 and 0.2, respectively. (The factor of merit of a given integration scheme is to keep k = k_eff/k as small as possible.)

Scaling the MHM-based integration scheme to high-porosity materials is not obvious. It has been shown that damage may extend under the MHM, leading to an increase in k_eff and to profile distortion upon subsequent wet cleaning. This observation highlights the fact that a more thoughtful selection of etch, strip and wet clean chemistries in relation to plasma parameters and processing sequence is key in choosing an optimal solution.

Focusing on improving the patterning performance of narrow structures, including damage and profile control, the following sections describe developments in plasma, wet clean and CMP processes in relation to low-k films.

Plasma damage

In damascene integration, etching of narrow structures free of profile distortion, faceting, k-value degradation, yield loss, and poor reliability performance presents the greatest challenge. As mentioned earlier, most of these problems originate from low-k patterning during exposure to etch and ash plasma processes, and are amplified throughout the entire BEOL process flow. To overcome this issue, several strategies are considered.¹²

One approach using sacrificial hard masks such as metallic and organic materials is currently being investigated to replace the conventional SiO₂ and SiC inorganic hard masks. Metallic and organic materials such as TiN, TaN and carbon-rich layers, for example, have a different chemical nature than porous SiOCH, and therefore exhibit better capabilities than conventional hard masks in terms of selectivity and faceting. The scheme does not completely prevent plasma damage from occurring during patterning, so requires a more fundamental understanding of damage mechanisms.

Low-k deposition and resist ash

Actual ash processes in copper/low-k integration can be divided into two main approaches. The first is a low-temperature, low-pressure, anisotropic photoresist strip based on oxidizing and reducing plasma chemistries. The flux of active species from the plasma allows stripping at low temperatures. However, the flux of species also penetrates porous carbon-containing low-k films, resulting in carbon depletion and subsequent hydrophilization.^13,14

The second strip approach is downstream plasma isotropic strip using reducing chemistries at high substrate temperatures, 270°–320°C.^12,15 For this approach, the effect of He/H₂ plasma at various substrate temperatures was investigated on advanced low-k materials (Figs. 2 and 3). The low-k film was deposited with a porogen-based PECVD process, and a thermally assisted UV cure removed the porogen and created porosity.

2. In a He/H2 atmosphere, the amount of water adsorbed into a pore network was measured with WEP (ellipsometric porosimetry with water source) and shown to decrease with increasing strip temperature.

3. TOF-SIMS depth profiles of as-deposited and He/H2 and O2 plasma treated films indicate shifts in carbon depth as temperatures change.

The studied He/H₂ plasma ash treatments appear to have inflicted no damage on the subject low-k films as they remained hydrophobic. The results indicate the absence of hydrophilization in the studied films. Moreover, it was demonstrated that a He/H₂ plasma over-strip may lead to k-value reduction because of an increase in porosity, without hydrophilization of the modified layer. The increase in porosity is related to removal of porogen residues, and is an indication that porogen removal from the pristine material was incomplete. However, instead of being detrimental, the modification might be beneficial because an increase of porosity can lead to a decrease of the k value of the films with a relatively small reduction in mechanical strength.

Low-k etch and wet clean

The essence of MHM-based patterning is indeed to decouple etch and ash plasma from resist stripping before etching the low-k dielectric. In a resist mask scheme, the low-k is first etched and then the resist stripped, a sequence that must be followed strictly. In contrast, in an MHM scheme, the desired pattern is transferred to the MHM and then one can strip the resist before etching the low-k, or etch the low-k and strip the resist afterward. In this case, both process steps are independent. Also, the lithography step parameters are independent of those of the dielectric.

This approach limits the number of times the film is exposed to plasma, while the etch process removes the part of the low-k film that was damaged during ashing. However, with increased porosity, the ash-induced damage extends under the MHM and therefore cannot be removed during etching (Fig. 4a). Either the damaged part remains after etching (Fig. 4c), or is removed during the wet clean (Figs. 4b and 4d), depending on the chemistry used. With an HF clean, for instance, an undercut appears (Fig. 4f), which impacts profiles and barrier step coverage. Also, less damaging etch chemistries might leave a polymer layer at the trench sidewall as well as on top of the MHM.

4. Issues related to MHM-based patterning may include ash-induced damage extending under the MHM (a), which can be removed with wet etching (b and d), remain behind (c) or be undercut with an HF clean (e).16

Attention must therefore be given to completely removing these polymer layers to avert electrical yield decreases, particularly at sub-100 nm dimensions. Figure 5 illustrates yield loss as line dimensions decrease from 150 nm down to 90 nm nominally. This phenomenon can be amplified depending on the low-k dielectric chemistry. For a k~2.5 porogen-based PECVD ULK film, this can be solved by using a post-etch cleaning step. With low-k scaling, the need to consider more efficient wet clean chemistries will become more critical.

5. Yield loss increases as line dimensions decrease from 150 nm down to 90 nm nominally. This phenomenon can be amplified depending on the low-k dielectric chemistry.

CMP-induced damage

To develop a sound methodology to study CMP-induced damage, we first needed an appropriate test vehicle. Ideally, a test vehicle must simultaneously take into account CMP consumables, barrier layers, and copper and dielectric films. One approach consists of generating checkerboard structures using a partial patterning approach, which leaves large open areas at the center and edge of the wafer. Such structures allow the characterization of both blanket films and integrated structures within the same wafer.

The choice of the metal layer interfacing with the low-k surface, which could be a copper barrier or an MHM, impacts post-CMP defect formation and subsequent hydrophilization.¹⁰ However, this damage mechanism is reversible. There are several ways to restore ULK material initial properties after standard CMP and post-CMP cleaning processes.

Annealing has shown to be valuable in removing residual organics and water absorbed at the ULK material surface after direct CMP (with no hard mask protection). However, because the hydrophilicity of the polished surface remains unchanged, it does not prevent moisture uptake, leading, in time, to an increase in the k value. Therefore, to restore hydrophobic properties and to stabilize the surface, organic molecules containing chlorosilane reactive groups (-SiMe_nCl_3-n) or hydrophobic methyl functions (-CH₃), have been employed in liquid, gas or dense CO₂ phases on the damaged ULK layers.

Each of these organic treatments is efficient in restoring hydrophobicity on post-CMP ULK surfaces. However, only one of them was able to maintain the low k value (comparable to the bulk ULK k value) and remain stable over time without inducing significant change in porosity.

It is worth mentioning that these repair solutions are only applicable to CMP-induced damage. Solutions consisting of improving ULK mechanical properties by UV cure, engineering the ULK/metal interface by inserting a "hard" protection layer, and carefully selecting the metallic layer are proposed as particular solutions.

More specifically, with TaN for a copper barrier and/or MHM layer, the use of a DPL with high mechanical strength is recommended to prevent CMP-induced damage. In general, the DPL consists of a dense SiCO:H film with k~3.1–3.5 and a Young's modulus of ~23 GPa or a PECVD SiO₂ film. The benefit of using a DPL in combination with TaN MHM has previously been demonstrated for medium-porosity PECVD ULK films. The DPL layer also appears to positively impact leakageand breakdown performances, without which significant changes in leakage current during thermal cycling are observed. This is attributed to moisture absorption and desorption into and from the ULK film as a consequence of scratching and hydrophilization during CMP polishing. This result suggests that the DPL protects the ULK film against this CMP-induced damage.

TDDB measurements have been performed with and without DPL. With DPL in place, testing showed an operating lifetime of more than 10 years. A very short median time to failure was observed with no DPL.

Post-CMP cleaning damage

6. For post-CMP cleaning of dense low-k films, ammonia (NH3) plasma is the standard. However, with low-k scaling, NH3 plasma (left) can cause severe field damage. He-NH3-based plasma (right) reduced the damage caused by copper reduction.

To curb the damage caused by copper reduction (evidence of plasma damage), a He-NH₃-based plasma was used. The result was a significant reduction in carbon depletion between trenches.

Because post-CMP cleaning using conventional NH₃ plasma is reaching its limit when porosity exceeds 25%, a dielectric surface pretreatment with helium plasma prior to NH₃ appears to be a good option for providing minimal damage and sufficiently good adhesion with a dielectric liner.

Conclusion

Selecting an interconnect solution requires an in-depth understanding of material properties as they interact with unit process steps. Most importantly, it requires establishing a clear link between these interactions and device performance and reliability. Today, for dielectric layers with a k=3.0-2.5, the goal is to decrease CDs while maintaining performance and reliability. For dielectric layers with k<2.5, the focus should be on developing ULK films with porosity <25%.