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Reducing risk by integrating configurable mixed-signal data converters
GUEST OPINION: An approach borrowed from the structured-ASIC world can be applied to mixed-signal data converters.
By Lior Amarilio, ChipX -- EDN, 12/2/2008
The growing need for integrating mixed-signal data converters into an SOC (system on chip) is pushing the industry to find better solutions these days. Many design teams that are expert in the digital domain are now facing a new challenge of integrating analog IPs. Luckily, the analog IP industry has evolved and grown rapidly during recent years, providing a solid base of IPs for integration. When focusing on data converters—one of the growing fields in analog IPs—one can find a large variety of converters, each specifically designed to meet a specific customer need. Nevertheless, the challenge involved in integrating mixed-signal data converters into an SOC remains high. Moreover, meeting the desired performance on silicon is not trivial, and introduces high risk for the whole project.
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An approach borrowed from the structured-ASIC world can be applied to mixed-signal data converters. The idea is to reuse the same analog building block by applying different configurations, where each one produces a unique, predicted, and characterized feature set. This approach dramatically reduces the risk involved in integrating new analog IPs into any new design, because it is better to use silicon-proven IP.
The goal of reducing cost drives designers to integrate more blocks into a single silicon chip. Analog IP integration in general, and data converters in particular, are becoming commonly integrated features in today's SOC. The positive side is that designers are facing a state where both DACS (digital to analog converters) and ADCs (analog to digital converters) are widely available from numerous IP providers. Because each converter has its own feature set, such as process type, number of bits, voltage swing range, power dissipation and more, the designer has to select the specific converter that best fits his design requirements and then go through the hassle of physical integration.
After selecting the desired IP block based on the design requirements, the integration process begins. The process of integrating an analog IP is not trivial for the digital designer, and poses a few risks. The physical designer has to meet all power ring requirements, and consider ESD structures and noise immunity to promise an operating data converter.
It might happen that even if one follows all integration guidelines, the actual measured performance of the data converters after device manufacture is different from the specifications. This kind of failure tends to take place where new analog IP is involved that was not proven on silicon before being included in the design. Moreover, when the integration process is not fully followed or a mistake takes place, a malfunctioning data converter can result.
Nevertheless, many times the integration does come up well, according to expectations. And luckily the integrated data converter operates according to the specifications in silicon the first time. When a new design comes to mind, many times the requirements of the data converter IP are modified as well. This requirement leads to selecting new IP and going through the challenge of integrating new data converter IP, along with the related risks.
Configurable mixed-signal data converter approach
The approach taken with configurable data converters eliminates most of the unknowns, and provides the benefit of re-using the same IP block for different feature sets. The configurable data converters provide the ability to select the number of data bits, tune the voltage swing, and trade power consumption versus frequency and output load (this is most important with the Current Steering DAC). In addition, this design is built for scalability, enabling concatenating two or more units. And single units can be concatenated, for maintaining phase alignment and amplitude matching.
The biggest advantage of such an approach is that this cell is fully characterized and silicon-proven for its entire feature set. This eliminates the potential risk of mismatch between specification and silicon performance involved in analog IP integration. Of course, one drawback exists—the dimensions of such a cell are slightly larger in comparison to a standalone IP, but after integrating them all together, this difference become almost negligible.
Using configurable data converters provides the freedom to implement different applications. One example may be different configurations of the same basic DAC IP block can enable the support of video encoder, using three DAC instantiations operating at rates from SD to HD television. Anther example may be that configuration using two pairs of DACs and ADCs provides the ability to create an IQ-matched signal pair for wireless-baseband AFE (analog front end).
Today's SOC designs are becoming richer in analog IPs. Using silicon-proven IPs reduces the risk involved. Using the structured-ASIC approach, where a configurable data converter block is proven on silicon and can be configured to meet different design requirements, we now have an almost risk-free approach for analog data converter integration.
| Author Information |
| Lior Amarilio is Chief Architect at ChipX. |
