Practical Chip Design

To most sensible physical design folks, the mysteries of operating and tuning lithography systems are just that: mysteries. You put in a set of patterns on the masks, and you get out a set of patterns on the wafer. Granted that the patterns on the mask have to be pretty fancy these days to deliver the patterns you wanted on the wafer, but that's the mask shop's problem. Unfortunately, as we move further and further below the wavelength of our only viable light source, this comfortable situation is breaking down. Some of the darker secrets of the lithography engineer's craft are beginning to become matters of interest to chip designers.

One case in point is lithography matching. Jim Wylie, senior technology director at ASML's captive computational lithography arm, Brion, points out that behind the closed doors of the clean room, lithography experts know that a modern scanner has many knobs on it, most of which are not discussed with chip designers. And if you put the same pattern into two scanners of the same model, each with its knobs set the same way, you will get two different results on the wafer. This ugly fact has led to a process known as lithography matching.

Tom Pye, senior director of strategic marketing at Brion, adds that there are two distinct approaches to dealing with this problem. Most fab managers opt for literal matching: they adjust all their scanners so that they all produce the same results out for the same pattern in. "Some managers take a different approach, though," Pye says. "They want every scanner optimized individually to give the best possible results, rather then adjusting them all to give the same results." In principle, that means that the fab is getting the best possible performance out of each piece of equipment. But it may also mean that the managers have to schedule particular masks to be used on particular scanners, instead of being able to rely on any combination of mask layers and equipment.

So far all of this dirty laundry can remain behind closed air locks. But as geometries get smaller, the response of a scanner to a particular group of knob settings becomes pattern-dependent. If the engineers tune all the scanners to give the same adequate result on a test pattern, they may all give different results—not all of them acceptable—on a different kind of pattern. This threatens the whole idea of matching.

In response to this problem, Brion today introduced a set of lithography matching software—LithoTuner Pattern Matcher and LithoTuner Pattern Matcher FullChip, that assist lithography engineers in tuning their scanners not just to a generic test pattern, but to the most critical patterns on a particular mask. Litho engineers would use the FullChip product to identify the critical patterns on a particular mask, and then use LithoTuner to adjust all the knobs on all the scanners so that they all produce the same acceptable result on those critical patterns.

This is a multi-variable optimization that cannot, in general, be accomplished with just the simple knobs like dose, illumination, and focus, Wylie emphasizes. It requires detailed knowledge of the design of the scanner to even know what adjustments actually exist inside the equipment, and it requires an accurate computational model of the scanner's transfer function. "Including actual data from the scanner, such as the Jones pupil [don't ask, but if you must, try here] significantly improves the model," Pye says. This is of course a fortuitous situation for Brion, living as it does inside ASML.

The new capabilities should allow litho engineers to retune their systems on the fly for each mask they are running, substantially improving results on the most difficult patterns. In addition, Pye says, the tools make it possible to tune the scanner not only to compensate for its own transfer function, but for the effects of downstream process steps such as mask, resist, and etch. The scanner is the only system in the front-end that can change its behavior as it moves across the field, making it in some ways the best place to deal with downstream issues that cause variations across the wafer.

So why do designers need to know about all this? To start with, it may become important for designers to know just how their foundry's litho engineers are tuning the scanners. If they are matching to a fixed test pattern, the foundry may simply not be able to achieve the variability control that a foundry with more aggressive tuning could achieve. And secondly, if the foundry is tuning to actual mask patterns, the physical design team should participate in selecting the patterns that are in fact most critical—not based on the geometry alone, but based as well on the electrical requirements of the design. This can avoid the classic example of misdirected energy, in which maskmakers and litho engineers struggle to accurately reproduce dummy metal or the designer's cute little logo. And so chip design teams are inevitably drawn deeper into the mysteries behind that sealed door.