Anablog

I had the pleasure of going to the TI power seminar I told you about a couple of months ago. It was really great. There were 8 topics and the only one I didn’t like was the sales presentation. EDN editors get comped to these events but everybody else had to pay 99 bucks to get in. I object having to pay for people to advertise to me. Interestingly, TI moved the sales pitch from the last slot to the one just before lunch, another telling indication, since I have to assume when it was the last topic people just walked out. Of course what was the last topic of the day, the z-transform math behind digital power also had its share of people walking out early. I hope the presenters understood that there were people that came from Roseville and Sacramento for this gig and they needed to get back as early as possible.

OK, enough sniveling about sales pitches, the vast majority of this seminar was fabulous. There was not a single presentation where I did not learn some interesting fact and yeah that included the sales presentation. TI had two FAEs from the Los Angeles area giving the presentation, while many of the TI local FAEs were in the audience. As I mentioned, they did not give the presentations in the order of the handout books. Much like the Fairchild power seminar a couple months ago, there was a spiral-bound book with the PowerPoint presentations and a perfect-bound book with the papers that the PowerPoint’s were based on.

Bob Mammano tells us about power factor correction.

After a free breakfast and some great coffee, the first presentation started. It was about power factor correction (PFC). Although Ken Ristow, the Silicon Valley applications manager explained that the material was not going on the web until the end of the seminar, I did find a pdf of the power factor correction presentation on the web. You especially want good power factor if you have to draw a lot of power from a wall outlet. A PF of 0.5 would only let you get 719 watts, whereas if you can get the PF up to 0.9 you can get out 1294 watts. As with all the presentations there were several valuable things to take away from the power factor correction topic. First was that any universal input voltage PFC design has to satisfy both Energy Star as well as EN61000-3-2 standards. The end result of that is that you can meet EN61000 with a power factor as bad as 0.72. But Energy Star requires a 0.9 PF. And you can meet that 0.9 PF and still have harmonic content that would violate EN61000. I asked the presenter, Bob Mammano if there was anyway to meet Energy Star with passive components. He said you could with really big inductors and chokes, but you could only do it for a specific voltage and load. You need active power factor correction if you are going to have universal inputs. Now since the power factor circuit is an extra stage, you want to maximize its efficiency. Most power factor correction circuits are boost converters. They boost the input ac (rectified) up to a voltage higher than the peak voltage. This allows the control system to draw a sinusoidal current that matches the phase of the voltage, providing the design with good power factor. So you can define a design parameter called boost factor that is the output voltage divided by the peak input voltage (not rms input, the peak of the rectified lumps, or ½ the peak-to-peak ac input). The deal is that the more you boost the input voltage the less efficient the converter will be. It will also have to be bigger and more expensive. The paper, written by Isaac Cohen and Bing Lu shows a flyback topology where the secondary output voltage is added to the rectified input voltage. The math works out so that this is the same as a plain boost converter, yet this separates the power paths, I wish I could remember why that was a good thing. So most slides after this was showing clever ways to keep the boost factor down so you can get good efficiency. The simplest was to just not make this a universal input. Then you can boost by the minimum amount, a boost factor of 1 and get 98.32% efficiency. If you boost by a factor of 3 then you are down to 92%. Other schemes were to have a switch for 120 and 240-volt operation. This allows you to keep the efficiency above 95%. Then again, you can just set the converter up to have a boost factor of one and then the intermediate buss voltage wanders from 100 to 350 volts and you let the downstream buck converters deal with that wide input range. One fascinating solution is to not boost the voltage but rather to buck it down. This means that there will be dead zones of input current whenever the input voltage is lower than the bucked output voltage, but it turns out you can still meet both Energy Star and IEC standards. Since the buck topology has a switch in series with the output capacitor you can soft-start this topology and prevent inrush, a huge advantage in my opinion. Efficiencies are above 96% from 90 volts to 270 volts in. They recommend buck style for anything less than 600 watts. I would have liked to see an application of a buck-boost topology like I wrote about in my last power article, but they only had ½ hour for this presentation. One great thing about this presentation was that it did not push a bunch of TI part numbers in your face—I only saw one that was in a figure. Oh, and one small complaint, all the schematics used the earth ground figure, including the ac bridge where tying the negative output to earth would blow up the diodes. Please people; use earth ground only for green wires and 10-foot copper busbars. All the schematics should have a little triangle for ground since it is only a system common, not an earth ground. The same goes for not using the chassis ground symbol.

Bill Strausser explains intermediate bus architectures.

The next topic was presented by Bill Strausser, also from TI’s LA office. He showed us how to make high-efficiency intermediate system busses. The paper this presentation was based on was by Rais Miftakhutdinov. It turns out that if you need a lot of voltage rails in the system and if you have a really narrow input voltage range it actually makes sense to put in another buck regulator between the ac to dc front end and the point of load (POL) modules. This converter is sometimes called a dc transformer since it often runs open loop. The converter knocks down the input 48 volts to 12 volts for example. Then all the POL modules have 12 volts in since they are not trying to go from 48 to 1.2 this makes the design of the module more efficient. Most of these intermediate bus converter modules are over 95% efficient so what you give3 up in this stage you can gain back when you make the final rail voltages you need in the system. These converters then to run pretty slow—100 to 200kHz, since the fewer switching event you have per unit time the lower your switching losses. You can use full-bridge, half-bridge and push-pull topologies, although the full bridge uses the transformer best and it also can clamp the primary winding to zero by turning on both low-side FETs at once. This is important for another major take-away I got from the seminar—since the secondary side of these converters have FETs used as synchronous rectifiers instead of diodes, this means the converter will work in both directions. If you drop the input voltage suddenly the switching secondary synchronous FETs will chop power into the secondary winding and that flows back to the primary and back into the input caps and circuitry. If the control system is smart enough, it can just bring both low-side FETs to ground to short the primary and prevent the secondary from sending power back. Other subtleties with intermediate bus converters (IBC) are that they can get stuck at half voltage on startup if there is a constant power load. To fix this the controller can start up at a higher frequency, say 400kHz and this makes the output inductor ripple smaller which allows the converter to sail past that halfway point and get to full voltage. The control system then kicks back to 100kHz. The presentation discussed some other issues like off-time control and things that, as always, means analog design is harder than it looks even for something as simple as an open-loop full-bridge. As always it is not the steady state, but the boundary conditions of starting and stopping and all the other things like voltage and current limits. The presentation ended with some chips that you can use to make these converters. There are a lot of times where you don’t really need tight voltage regulation and I would recommend this topology and control system when you can just use an unregulated output form a high-frequency transformer.

The third presentation was given by Bob and was from a paper by John Rice, Dirk Gehrke and Mike Segal. It was about using spread-spectrum clocks on your switch-mode power supplies so you can pass FCC and IEC emissions tests. They had a lot of nice charts that showed reduced EMI over the CISPR regulated bandwidth of 150 kHz to 30MHz. The problem that I have with all these charts is that they imply dithering (varying) the clock on the power supply will reduce EMI. It does not. It only spreads it around and therefore reduces the measurement of EMI by the spectrum analyzer. It is essentially cheating the test. Everybody does it though, so there is no shame in using if it means you can pass FCC and get your product to market. They showed a couple chips you can use to dither the clock. They pointed out that if you sweep the frequency with a sine wave that means the clock lingers at the extremes (the slow-moving peaks of the sine wave) so the frequency response gets little “bat-ears” on the edge of the swept plateau. So you can use a triangle wave and reduce those ears, making the spread frequency plateau flatter. Best of all you can use an exponential waveform that is called a Hershey’s Kiss waveform and this keeps the frequencies optimally flat. I learned about this for my upcoming story on oscillators. I was told that Lexmark owns the patent on this Hershey-Kiss modulation and that a chip company has to pay them to use it. A fellow in the audience asked if you could use a PBRS (pseudorandom binary sequence) to generate the clock. It turns out that is exactly what Linear Technology does in its spread spectrum clock oscillators, I know because I got briefed by Doug LaPorte, their design manager, just last week.

This Hershey-Kiss modulation makes for a flat spread spectrum plateau.

Forth up was that sales presentation. There were 20 slides and 8 of them were marketing fluff about how great TI is. We know TI is great, just tell us what parts you have. Here they are: UCC28610 flyback controller, UCC28230 intermediate bus controller, UCC25600 resonant mode controller, TPS54160 3 to 60 volt in buck, TPS55383 Dual 3-amp non-synchronous converter, TPS40197 VID buck, USD9240 system controller (PMBus), TPS23754 power-over-Ethernet, TPS2500 USB switch and boost converter. See, that didn’t take nearly a half an hour and now we can go to lunch early.

After lunch, presentation 5 was a great tutorial about the boost converter. Bob gave this one based on a paper by Brian Lynch. The cool take-away was that since a boost converter builds up current in the inductor in one half-cycle and then dumps that into the load when the switch opens there is an inherent right-half-plane zero. Since any control action during the on time is delayed until the off time the output response is in the opposite direction of the desired correction. The presentation went on to describe continuous conduction mode and discontinuous conduction mode (CCM, DCM). Bob pointed out that for a fixed-frequency converter all you can really change is the inductance value. He pointed out how synchronous FETs work great in DCM since the current goes to zero every cycle and you can put up with slow recovery. This is a very solid presentation. The conclusion was that a DCM converter has wider bandwidth and the expense of lower efficiency. The CCM provides some ease in compensating the feedback loop.

The 6^th topic presented was on the PMBus. It was given by Bill based on a paper by Kurt Hesse. He showed the benefits of the PMBus, a serial interface for power supplies that has developed into a standard for control and monitoring. Having power controllers with PMBus is almost as cool as having a GPIB connection. You can control voltage and set current limits, you can specify rise times and do margining to account for load or to test for system reliability. There are group commands you can set up for several slaves and then launch all the actions with a single command. Now the problem with PMBus is not technical, it is legal. I pointed out to Bill that Power One claims that PMBus violates its patents and has won a court case over this issue. I asked Bill if TI would indemnify me from a Power One lawsuit if I used their PMBus chip. Bill smiled. He said he would have to drag out some legal boilerplate and read it word-for-word. I think this means the answer to my question was “no”. So you might want to steer clear of any PMBus designs in the near term, at least until the issue is settled. There are rays of hope, but this looks as ugly as the SCO Linux lawsuits.

Bob took over for the seventh presentation, which was about using a high-voltage storage bus to improve the holdup time of your system. The big deal here is that energy is ½CxV, so if you store energy at 88 volts instead of 39 volts, you can go from 40 capacitors to 3 capacitors. As you might expect, TI makes a really cool chip that implements a really cool little power section that fits in a few square inches of board space. It is a non-isolated flyback that uses three FETs, and an inductor and a couple of diodes. It draws power from the system bus and boosts the voltage up to charge the holdup caps in this little converter. Once the high-voltage capacitors are charged up the converter just idles, popping charge in on rare occasions just to top off the caps as they leak down. Then if the main system bus sags or drops out, the converter moves charge from the high-voltage caps and transfers it to the main bus capacitors to holdup the system voltage as long as possible. It is a neat little circuit. Bop pointed out that you could use a buck-boost topology but it makes for a more complicated controller and you need four FETs and a larger inductor. This presentation was based on a paper from Jean Picard. He concludes that a PFM (pulse frequency modulation) hysteretic converter results in low complexity. He notes that a voltage mode buck with feed-forward in holdup mode gives a simple circuit, small size, and good transient response. And yes, you mix in a ramp in the holdup mode to prevent those dreaded sub-harmonic oscillations. Great stuff.

The last presentation was a digital power tutorial. As I noted, many people had their eyes glazed over by all the math and left early rather than slog it out. Too bad, Bill did a great job with this presentation based on a paper by Mark Hagen. It was very similar to a paper I saw at the Darnell digital power forum. Now Mark presented at the Darnell conference on the subject “When Will Digital Power Become a Mainstream Power Technology?” but the paper that was most like his was from the Primarion group at Infineon. As with most digital power presentations, this one had humor, like when it said: “Switch-mode power supplies (SMPS) have always had a digital component; the have a control-effort update interval equal to the switching period.” Sigh. Sorry, there is nothing digital in an analog power supply controller. There is no switch period in a hysteretic controller and what about the variable frequency converters? A PWM signal is not digital since its amplitude can vary and its resolution is infinite, only limited by the noise floor of the chip. Bill said that the drive to the FETs in an analog converter are digital but I take exception to that as well, that is an interface function and interface chips are analog. OK, so like the Primarion presentation, this one pointed out that the old s-place control theory you know and love doesn’t work, you have to transfer everything to the z-domain. This takes a lot of math but TI has been nice enough to make this software called the Fusion Digital Power Designer that you can download for free and it will do all the math. See, rather than put a tweak box on the compensation node of an analog chip, you have to program digital coefficients into the loop compensation filters in a digital power part.  So TI did all the hard work and you can just play with this GUI and see what happens to the response. Of course, since a lot of digital power has non-linear gain you can’t hang a Ridley or Venible across the output and get a real gain and phase plot. You can ring it in time domain and see how stable it is there but that is a little scary. What the TI software does is all the math to convert back to a form that can be solved and then you can get the gain and phase plots on the screen. I guess if you don’t do any non-liner stuff in the chip you might be able to use a network analyzer to see if the software simulated your circuit correctly. The problem is that all the digital power folks brag about how cool it is to have non-linear response so you can boost the gain and vary transient response and noise and all this other hoopla. All it does is scare me. I want a single dominant pole in my control systems, thank you very much. I see they have stopped bragging that digital power is more efficient since all that was based on is turning off phases in a multi-phase controller. Analog parts can do that as well. Now one really cool thing that digital power can do is auto tuning. What TI did was put a little sine table and DAC in the part to add an excitation in the loop just the way a Ridley or Venible does when you hook it up to an analog part. Then the part evaluates its response from the all the monitoring functions these digital parts love to build in. This lets the part establish the transfer function of the plant, which is the power stage. The practical thing you might do is evaluate the particular value of the output caps or may you could sense that the output caps were degrading then adjust the compensation. When you finally get to a point where the power supply is out of spec, I assume you could raise a flag or send a message to indicate that the part was in trouble. The people at startup Powervation want to use 2 DSPs to do this auto tuning on a cycle-by-cycle basis. Me, I am old school, I don’t want my power supplies to think, and I certainly don’t want to have a talk with them. I just want then to work. All the marketing types are raving about digital power but all my FAE buddies say that nobody is using it in big volumes yet. We will see what the future holds; if anybody can make a compelling application then it is Texas Instruments.

This digital power business brings up a question I want to throw out. Intusoft, the SPICE people, called me last year claiming they had a SPICE that could develop DSP code for digital power. I could never get a straight answer about what SPICE has to do with a DSP. It turns out that what Intusoft has done is make a z-transform module the way that TI has done in their Fusion Digital Designer. Intusoft did this for the great folks at Microchip, who have both DSP and state-machine digital power. So what this does is allow you to simulate the filter coefficients of a power supply, or anything else for that matter, and plug that into your DSP code. My problem is that Intusoft calls it SPICE. I’m sorry, SPICE stands for simulation program with integrated circuits emphasis. It uses matrix math to solve Kirchoff’s laws. So you can call a z-transform program a simulator, or a translator and yeah, once you get out of the z-domain and into the s-plane I guess you plug that into SPICE, I just don’t think Intusoft should call this SPICE. That name has a very specific meaning and saying you are using SPICE to generate DSP code is pretty misleading. Do you agree or is it OK to call a Z-transform front end a SPICE simulator?

Back to the TI power seminar, it was a day well spent and I got to meet some great power engineers and learned a lot. I cannot encourage you enough to check it out; there are still a few cities left:

04 Dec 2008            Orange County, CA | United States

10 Dec 2008            Tucson, AZ | United States

11 Dec 2008            Phoenix, AZ | United States

And they will be in Europe and India in March and April of 2009.