The Fine Print

For the SEMICON West Daily News, I reported on the Tuesday afternoon Device Scaling TechXPOT, which featured presentations and panel discussion on lithography options at 22 nm. Although I wanted to include comments from moderator Lars Liebmann, I had to cut back to make the story fit on one page (all the news that fits, right?). Granted, lithographers and their suppliers have a mighty difficult task ahead of them, but Liebmann had a particular knack for making each technology candidate look bad — and for upsetting several participants and attendees along the way.

This TechXPOT session offered up six speakers to present on six potential lithography routes: immersi...Read More

Carl Zeiss SMT (Oberkochen, Germany) recently designated Schott Lithotec (Jena, Germany) as its latest Supply Chain Partner. The official press release talked about what the new status meant: “expanding our long-term relationship and business”, “we will jointly fine tune our technologies”, and strengthening the “historic business relation”. But, particularly with Schott Lithotec’s highly pivotal role in the viability of high-index immersion lithography, I was curious to know what the Partner designation really meant.

There ...Read More

Molecular Imprints Inc. (Austin, Texas) put out a press release today announcing the appointment of Ben Eynon as the company’s vice president of marketing and business development for semiconductors. No wonder Sematech folks were being so cagey in May when I asked when Eynon would be taking over from Mike Lercel as lithography director. Eynon was supposed to be taking over in May, but Lercel was still holding the reins at the Litho Forum that month in Bolton Landing, N.Y. It turns out Lercel already knew then that Eynon was leaving, but couldn’t say anything before Molecular Imprints made its announcement. In fact, Eynon has already been at MII for about a month, he tells me.

The move was a nat...Read More

In my June 11 Lithography Report, I asked readers for feedback on the International Workshop on EUV Lithography, a new conference organized by Vivek Bakshi and EUV Litho Inc., which took place last week in Maui. I got such a detailed and informative response from one reader that I wanted to share it with you here.

So this latest installment is a guest post from Kenneth Goldberg, a physicist at Lawrence Berkeley National Laboratory (LBNL) who works on EUV lithography issues, primarily optics testing (EUV interferometry) and EUV actinic mask inspection (AIMS-type and scanning). He attended the conference, where he led a mask ins...Read More

It’s interesting to hear the same person who made such a push for immersion now making a similar case for electron-beam direct-write (EBDW) lithography. Given his success with immersion, not to mention his considerable experience in the industry, it’s hard not to listen to what TSMC’s Burn Lin now has to say about maskless technologies, especially when he says himself that he has been an “optical bigot” most of his life.

And he makes some awfully good arguments: the ability to cluster tools to give a chipmaker just the amount of throughput it needs or can afford; a much smaller footprint than EUV; and the clincher: cost. There’s the potential for a multiple e-beam tool to have about the same cost as an immersion scanner, Lin contends, both...Read More

At Sematech’s Litho Forum this week in Bolton Landing, N.Y., the proponents of various next-generation technologies are duking it out to demonstrate worthiness as water immersion successors. The session on high-index immersion lithography just wrapped up, and it ended with a solid thud.

EUV and double patterning sessions were presented in full yesterday, but high-index was split between yesterday afternoon and this morning. Although yesterday’s high-index presentations were interesting (including updates on resists, fluids and lens materials), today’s updates from the lithography tool manufacturers really got to the important question: Is high-index immersion lithography in fact feasible?

When Intel speaks, people are generally interested. And when the überchipmaker says it won’t be using EUV lithography to introduce 22 nm technology into its chips, people take notice. And so, like many others, I was quick to click on yesterday’s headline, “Intel: ‘EUV Facts Don’t Add Up’ for 22 nm in 2011.” It’s somewhat early still, but so far the article has garnered close to 3× as many page views as the next most popular article on our site this week (a story about Hynix cutting its capital spending, in case you’re interested). I’m not surprised, and actually went to our web analytics tool today specifically to confirm my suspicions.

Although plenty of people will tell you that the switch from 300 to 450 mm wafers is going to have to happen at some point, and most likely around the 2012 timeframe, the conversation is far from over. I understand the reluctance to embrace this change from a tool manufacturer’s point of view, and probably even more so from a wafer supplier’s point of view, but I hadn’t thought about the impact that 450 mm wafers would have when it comes to particle contamination and the already shrinking lithography process window.

I was out at Sematech’s Surface Preparation and Cleaning Conference (SPCC) last week in Austin, and had an interesting conversation with a wet cleans engineer at a major memory manufacturer. The point he made was about how much more importan...Read More

The Molecular Imprints folks seem to have very bright outlooks on their future lately – they speak in a way that is more upbeat than I’ve heard them in the past, like they’re finally really getting somewhere in the semiconductor industry. “The semiconductor industry is beginning, I think, to pick up a lot of interest,” CEO Mark Melliar-Smith beamed. “If you look at the presentations that are going on at SPIE… we’ve got Toshiba, Hewlett-Packard, Samsung, IBM and Seagate. It’s a real who’s who of memory and technology companies. And it’s a very impressive list.”

And now, of course, there’s Sematech. When I had this conversation with the folks at Molec...Read More

As is often the case during the nighttime panels at SPIE, there was a fair bit of silliness in Tuesday night’s panel discussion, “Future Projection Lithography: Optical or EUV?” It’s a serious enough question, but after a very long day of listening to detailed technical presentations, attending customer/supplier meetings, and perusing the exhibit floor, these leaders of the teams trying to find answers to extremely difficult lithographic challenges were ready to loosen up a bit.

The tone was set very aptly by IBM’s Kit Ausschnitt, who entertained the audience with a reading of his latest musical adaptation — this time, with apologies to Bob Dylan, with Blowin’ in Our Wind:

The American National Society of Professional Engineers has officially designated this week Engineers Week. I, for one, don’t want to miss this opportunity to give a big virtual hug (I’ll even throw in a virtual smooch) to all the outstanding lithography engineers working so hard to keep us on Moore’s Law.

How many times have we all heard about the imminent demise of optical lithography? If not for the very smart tricks developed by very smart engineers, it would’ve been dead long ago. And yet it’s as alive as ever. The engineering issues are getting tougher and tougher, and it’s an incredible amount of work that continues to go into developing such creative solutions in illumination, OPC, phase shiftin...Read More

Sematech (Austin, Texas) announced yesterday that it achieved its goal of single-digit mask blank defects for extreme ultraviolet (EUV) lithography. The achievement of eight defects combined from the substrate and the multilayer translates into a defect density of 0.04/cm², and also surpasses the consortium’s goal for the end of 2007.

According to Sematech’s commercial blank roadmap, which the consortium first developed in 2002 to chart the progress being made in defect-free mask blanks, the target for defect density by the end of 2007 was 0.06/cm², or about 12 defects. The roadmap dictated getting to 0.04/cm² by the first half of 2008. The cut-off size for those defects, according to the roadmap, is 60 nm (PSL equivale...Read More

The National Institute of Standards and Technology (NIST, Gaithersburg, Md.) and NIL Technology (Kongens Lyngby, Denmark) are conducting a global survey on nanoimprint lithography, and I said I’d do what I could to help get the word out there. Together, the two organizations are looking to identify the major roadblocks facing the implementation of nanoimprint, looking specifically at the materials and metrology needs. So if you think you might have some input, please take the survey.

NIST’s Christopher Soles tells me that he plans to keep the link open to the survey for at least a month, and will mention the survey at the Advanced Lithography conference later this month to try to generate more interest.

Cymer Inc. released its quarterly and annual revenue results earlier this week. I won’t regurgitate all the numbers for you here, but let you read the release directly (hint: follow the link). But I did want to comment on what I see as a few key highlights of the release and related conference call.

Given the company’s powerhouse status in providing lightsources for such emerging technologies as immersion lithography, double patterning and extreme ultraviolet (EUV) lithography, it was interesting to hear its executives’ perspectives on the marketplace. Although analysts and other company execs are painting a pretty gloomy picture for 2008 capital spending, and the laser system outlook is really no exception, it’s interesting to see the potential growth at the leading edge &mdas...Read More

I have been woefully negligent about keeping up with this blog, and for that I apologize. I hereby pledge to do my darndest to stay on top of the goings on in the lithography world — not only by formulating blog postings in my head, but by actually typing them out as well.

One of the things that’s been keeping me so busy lately is the behind-the-scenes work on our next lithography webcast, which will examine what kind of shape immersion lithography is in, and what’s needed for the final push to high-volume production. Over the past couple months, we’ve managed to pull together a really great lineup of panelists: Burn Lin of TSMC, Kurt Ronse of IMEC, Bryan Rice of Sematech, and Soichi Inoue of Toshiba Semiconductor.

On...Read More