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IC Design

Comprehensive coverage of the challenges IC designers face, the most significant technologies produced by providers of EDA (electronic design automation) tools and IP (intellectual property) cores, and the design methodologies other IC designers are using to become successful.
Top Story
Top Story

Through-silicon vias, oxide bonding accelerate 3D IC development 12/1/2008

Stacked-die assemblies are moving beyond wirebonding for die-to-die interconnect. But are design tools ready for them?

News

Researchers explore nonvolatile resistive RAM as flash replacement 11/13/2008

Researchers are leaving no stone unturned in their attempts to find an alternative nonvolatile-storage mechanism that can scale to processes smaller than 32 nm—the point at which, many fear, flash may run out of gas.

“Crystal” oscillator comes without the crystal 10/30/2008

Silicon Laboratories is offering a new class of oscillator as a frequency reference. The all-silicon Si500 series uses neither a MEMS (microelectromechanical-system) frequency system nor a crystal, but it challenges crystal oscillators in the high-volume-frequency-reference sector. After you order the compensated-LC oscillators, you receive samples within two weeks with a minimum order of 75 un...

Cadence, Tessera team to optimize illumination for 22-nm lithography 10/8/2008

Using diffraction masks in the stepper's light source to create custom illumination patterns, the companies claim a substantial opening of the process window.

TI driving development, ratification of IEEE 1149.7 embedded system standard 9/2/2008

To allow developers to easily test and debug products with complex digital circuitry, multiple CPUs and applications software in products such as mobile and handheld communication devices, Texas Instruments Inc, a key member of the IEEE working group, said today that it is spearheading the effort to ratify the IEEE 1149.7 standard, which is a new two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.1 technology.

Agilent, NVIDIA accelerate signal integrity simulations 8/27/2008

To accelerate signal integrity simulations faster than previously possible, Agilent Technologies Inc said Tuesday afternoon that it is working with Nvidia to develop a commercial software release of a GPU-enabled Advanced Design System Transient Convolution Simulator, based on Nvidia’s Compute Unified Device Architecture-based GPU.
In-Depth

MEMS-based inertial sensor is not your grandfather's gyroscope 12/1/2008

The IC Insider looks at a MEMS-based gyroscope in microscopic detail, and finds that the ingenuity in this sophisticated sensor goes far beyond the process technology used to sculpt its mechanical features.

DDR3 SDRAM exposed: Inside a bleeding-edge, blazing-fast memory device 11/3/2008

The IC Insider reveals the densely packed real estate and impressive clock-synchronization circuitry that allow Samsung's 1-Gbit K4B1G0846D-HCF8 to achieve its 1066-Mbps data-transfer rate.

Multicore: the future of SOCs? 10/30/2008

Will systems on chips follow server CPUs down the road to having many identical processor cores on a die?

A turn-off: Power management complicates life for verification engineers 10/16/2008

Advanced energy-saving techniques can cause vast difficulties in the verification process.

Lithium-ion-battery-charging IC powered by charge-transfer, control innovations 10/1/2008

The IC Insider: Reverse engineering the Maxim MAX8814ETA 28V linear lithium-ion battery-charger IC.
Experts

Reducing risk by integrating configurable mixed-signal data converters 12/2/2008

An approach borrowed from the structured-ASIC world can be applied to mixed-signal data converters.

From lithography to test 11/27/2008

The need for the OPC DFM technique is becoming increasingly important as lithography companies turn to double-patterning as an interim approach that will serve until EUV lithography becomes available.

Making ASICs gel 11/18/2008

The enormous complexity possible in ASICs today has had a damping effect on design starts. Many in the industry simply can’t afford to design the chips their customers want, and that their foundries can easily fabricate. We postulate a design flow that, by focusing on identifying the customer’s behavior-level requirements and mapping them onto a proven platform, reduces design complexity and breaks the logjam in ASIC designs.

Tech innovation addresses societal, environmental challenges worldwide 11/13/2008

Intensive research and development in nanoelectronics and nanotechnology is critical for tackling societal and environmental challenges facing the world today.

Third-party IP: placement, blocks, and clocks 10/30/2008

Tapeout: Questions to ask IP providers regarding placement, rotation, embedded blocks, and clocks.
DesignIdeas

Save valuable picoseconds using ECL-wired OR 5/15/2008

Substituting wire-OR connections for an XOR/XNOR ECL gate allows the circuit to meet stringent timing contraints.

CPLD connects two instruments with half-duty-cycle generator 10/11/2007

A clocking circuit programmed into a CPLD generates a synchronizing pulse for a slower instrument at half the duty cycle of a faster instrument.

VHDL program enables PCI-bus-arbiter core 9/13/2007

A simple VHDL program enables microprocessors or DSPs to act as PCI-bus masters.

Use SystemVerilog for coverage metrics 3/29/2007

SystemVerilog constructs suit RTL design, high-level modeling, testbench creation, and assertion specification.
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Events

JEDEC Partner Programs at CES 2009

Dates: 1/8/2009 - 1/8/2009
Location: Las Vegas, NV

ITAC and GSA Conference

Dates: 4/14/2009 - 4/15/2009
Location: Ontario, Canada


Blog

Practical Chip Design

Want to talk about verification with assertions? Accellera does

We offer the following note as a public service to the verification community and to the Accellera committee. "Multiple industry studies have... 

Why chip designers need to know about lithography system matching

To most sensible physical design folks, the mysteries of operating and tuning lithography systems are just that: mysteries. You put in a set of pat... 

Cadence pulls together the pieces for 45, 32 nm design

There have been so many point issues with advanced digital process nodes that the resulting scramble to come up with solutions has been less than o... 




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NEC Electronics America: Gate Array Resources

Find all the resources and tools you need from NEC Electronics, the number one supplier of 32-bit microcontrollers and gate arrays. With more than 5,000 device types, NEC Electronics offers innovative solutions and the support you need to make your design a success.
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