News and New Products

Strained SOI 300mm Wafer Produced

By Steve Bush -- Electronics Weekly, 12/10/2004

French wafer technology player Soitec and ASM, the Amsterdam-based substrate equipment company, claim to have produced the industry's first 'industrially manufactured' 300mm strained silicon-on-insulator (sSOI) wafers.

"The samples take this project beyond R&D evaluation and into the next phase of industrialization, enabling Soitec to make these wafers available for developing ICs at the 45nm technology node," said Carlos Mazure, Soitec's CTO.

Based on Soitec's Smart Cut process, the sSOI wafers exhibit a strain value of 1.5GPa (gigapascal) with homogeneity of ±7 percent over the wafer, according to the company.

The recorded strain corresponds to a silicon lattice deformation of almost 1 percent. The strained silicon layer thickness is 20nm with homogeneity of ±3 percent and a surface roughness comparable to that of premium bulk silicon wafers.

"Internal testing has shown that the Soitec sSOI wafers maintain their strain at temperatures up to 1,100°C, offering a process window sufficient to accommodate CMOS integration thermal budgets," said Soitec.

Electronics Weekly is the London-based sister publication of Electronic News.