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Flash: Moore's Law and Then Some
By Jeff Chappell -- Electronic News, 7/12/2005
SAN FRANCISCO – The density of microprocessors may still double every 18 months, but that's pretty pokey compared to flash.
If there was any doubt that the chip industry is now a consumer driven one, the news from this year's Semicon West should lay them to rest. It's hardly a news flash. Or is it?
Both front-end and backend tool vendors here are talking about how flash memory is driving leading edge technology, be it process or test. Perhaps it's not surprising, given the growth of the consumer segment, but that growth has made flash technology a driver for Moore's Law, and hence the supply chain, even more so than logic or its cousin DRAM.
Both Applied Materials Inc. and Agilent Technologies Inc.—companies at opposite ends of the chip equipment market – rolled out products today with their eyes on this growing market. As Applied CEO Mike Splinter put it this morning: "new growth has to come from the consumer and the emerging consumers … in the third world."
And that growth is manifesting itself in the chip equipment realm through flash production. As Gayn Ericson, VP of memory test at Agilent observed, more flash will be shipped this year, in terms of the number of transistors involved, than has been produced in the entire history of flash production to date.
Consequently, it is flash that has taken over from the MPU and DRAM as the driver of leading edge technology, noted Ashok Sinha, VP and GM of Applied's etch products group. While other technology has fallen behind, flash transistor density doubles every year now – twice the rate of DRAM – and ahead of Moore's Law, which states that density doubles every 18 months.
Sinha also noted that Applied has customers developing 32Gbit flash memory, and customers that plan to convince makers of MP3 players to replace micro drives with high-density flash. And it was a flash memory supplier that served as the first beta site for Applied's latest etch chamber, the Centura AdvantEdge.
But the annual density doubling in flash transistors is nothing new; it hass actually been going on for the last four or five years, noted Mike Hegarty, a global product manager for etch products at Applied. Etch has proved a challenge as this density has grown; flash transistor gate stacks currently are up to six layers, and Applied has participated in demonstrations with as many as 10 layers in a gate stack, he said.
Furthermore, flash chips are already using hafnium-based high k gate dielectrics; it will likely be flash that adopts even more exotic transistor technologies beyond the 45nm node, such as tri-gates, Hegarty suggested.
Applied says the advantage of AdvantEdge is edge exclusion – or lack thereof. Typically, edge exclusion on a 300mm wafer is 7mm to 8mm. Applied says its latest etch chamber can push that out to 2mm, while also improving critical dimension control to less than 3nm – allowing chipmakers to squeeze more die out of each wafer.
"The last 8mm of the wafer, is actually 10 percent of the overall surface – there's a lot of real estate that can be utilized," Hegarty noted.
This improved control in etch should extend Centura beyond the 45nm node, he suggested. Having proved itself on flash, it will be ready for high k adoption in logic. Logic makers primarily are looking at strained silicon and other substrate engineering methods to get the performance boost they need at the 65nm node; logic won't see high k gate dielectric in production until at least the 45nm node, Hegarty suggested.
"Our customers have struggled with the ability to etch high k in normal etch processes," he said. "So we began focusing on high temperature etching." Now Applied can offer a drop-in solution with its AdvantEdge chamber, he added.
Sinha, speaking during Applied's annual analyst event this morning, said that Applied already had 40 AdvantEdge chambers installed in the field in volume production. "And they've done fine over the past few weeks," he added. He expects Applied to double that number over the next six months.
Flash Provides a Challenging Test
Meanwhile, Agilent today took the wraps off its Versatest V5500, aiming at the burgeoning market for testing flash and multi-chip packages (MCPs) – both being largely consumer-driven applications at the moment. As Agilent's Ericson put it, the growing prevalence of stacked packages and MCPs makes for "some scary test challenges."
It's not uncommon for the latest generation cell phones to incorporate DRAM, SRAM, NOR and NAND chips in one package. "There's not phones being designed, in terms of advanced (3G) phones, that don't have MCPs in them," Ericson said.
He noted that from a test perspective, this involves testing for known-good-die, but also a lot more. The different types of memory involve different timing domains and operating speeds, for example. And there's no existing test fixture designed to access a module containing four different types of memory and four or more chips.
But Agilent says it can test these very types of MCPs with a single insertion, as well as do it in parallel.
The V5500, with what Agilent has dubbed its Programmable Interface Matrix circuitry, features a whopping 16,384 pins per test head. It is designed to fully utilize x320 test handlers in order to test up to 320 NAND devices in parallel, or up to 256 high-pin-count NOR and MCPs in parallel.
Ericson suggested that the tester could test up to 512 NAND flash devices in parallel, but that test handlers don't exist yet for that many devices.
When testing MCPs, the V5500 tests each die within the package serially; only a subset of the total I/O pins required to test the high-pin-count MCP is used to test each individual die as a result, according to Agilent. The tester's resources are subsequently coordinated via the Programmable Interface Matrix, minimizing the hit to overall test time, the company says.
Ericson said that the company currently has two customer beta sites lined up for the V5500, and that it plans to ship those beta testers later this month.
