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Start Up Runs End Around Mask Correction Tech
By Jeff Chappell -- Electronic News, 10/3/2005
A Mountain View, Calif.-based startup says it has a replacement for resolution enhancement software; one that it claims can get mask correction right the first time.
Luminescent Technologies Inc. today at the BACUS conference in Monterey, Calif., unveiled its first product, Explorer, the first iteration of what it calls its inverse lithography technology (ILT). "By inverting we get it right the first time," said Andrew Moore VP of marketing and business development for the company.
The "it" that Moore was referring to was the photomask, or rather the mask data. With production fabs now churning out devices with 90nm feature sizes, the industry has been fabricating features smaller than the wavelength of light used to create them for the last several technology nodes.
As a result, the industry has resorted to a number of methods to print those features correctly on a wafer, collectively known as resolution enhancement techniques, such as optical proximity correction (OPC). In simplest terms, techniques like OPC involve adding features to the mask – features that ultimately bear little resemblance to the resulting pattern – to in essence trick the light into creating the desired features.
OPC and other methods can add to mask costs and fabrication costs; the more OPC involved, the larger the overall size of the data file used to fabricate the mask. In some cases, with a complex leading-edge mask pattern, it can take a week or more of processing time to compile the data for a photomask – just one layer of a chip. If a respin is necessary – if the mask needs correction – the time and cost is compounded.
"It takes a lot of labor to use these approaches," said David Fried, CEO at Luminescent. Fried came to the startup after a 15-year stint at Applied Materials Inc. in a number of senior executive posts. "In some cases chipmakers will have script writing teams that are 20 or 30 strong to get the software ready to write the mask.
"They're not getting the kind of results that they need, though -- the pattern fidelity and the process window," Fried said.
To avoid costly respins of the mask, as well as segmentation scriptwriting, Luminescent says it can take the pattern as created by the chip's designer in a standard GDS file, then do the math to invert the pattern to produce a standard chrome-on-glass mask, already corrected for subwavelength features. Because it retains the GDS format, the technology is plug and play with standard process flows, according to the company.
With 65nm designs, Luminescent says it can avoid line-end shortening and corner rounding that sometimes happen with OPC-derived masks, and has the customer data to back that claim up. The company also says that they have performed full chip runs, and have been able to print features down to 45nm, features that cannot be printed with standard resolution enhancement techniques.
"We work with the light to get what you want on the wafer," Moore said.
It sounds simple, but the math involved is very complex, says Fried. Papers on the idea date back at least to 1981, and people in the industry have been working on the approach for a long time, he said. Luminescent claims to be the first to finally figure out how to do it effectively.
If customers chose to calibrate their designs for the particular photoresists that they are using, that usually takes a day; otherwise, set up for the company's Explorer product is rather simple; a user simple plugs in the exposure wavelength, sigma and numerical aperture data, and a mask file can be ready that same day, according to Moore. With resist calibration, another day is usually required.
While the GDS file size produced by Explorer depends on how detailed the design in question is, pretty much in call cases, it produces a less wieldy file than a corresponding OPC-derived mask, said Fried.
Explorer, the company's first product, can address any layer within a chip, but typically it has been applied to the first four layers, the device layers: contacts, active, poly and metal one. The company plans to have a beta application that can address an entire chip in the very near future.
Luminescent also announced today that it was involved in joint development program with Cypress Semiconductor Corp.'s R&D division, Silicon Valley Technology Center (SVTC). The companies plan to install Luminescent's ILT products in the research fab to develop 65nm designs and smaller. Luminescent first approached Cypress two years ago, and the companies have already created test masks and printed wafers entirely with Luminescent's ILT, they said.
