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Help Wanted: ES Level Evangelist to Drive EDA Growth
By Ann Steffora Mutschler -- Electronic News, 2/8/2006
In a rare moment of solidarity, a panel of industry executives agreed that the EDA market is indeed stagnating, and instead of focusing on the fact they are stuck, they focused on next steps to take.
Quite plainly, Gary Smith, chief EDA analyst at Gartner Inc., said, “Yes, we are stagnating.” He went on to explain that two years ago, the firm found that 27 percent of design engineers were using in-house-developed tools. Accounting for about 10 percent to 12 percent of those as power users that have always built their own tools, there are still a significant portion of mainstream users are being forced to use in-house tools, which are typically electronic system (ES) level tools because they are not available commercially.
This is not a new phenomenon, Smith reminded. “In the late 80’s, we went from gate level to RT level, revenue flattened out, Daisy-Mentor-Valid [the top EDA companies at that time] produced nothing that was worth seeing at DAC, and the same thing is happening again.”
As a result of that methodology shift and the current one to ES level, industry leaders will change, he explained. “We are going to lose some of the leaders because they are not leading.”
In terms of industry growth, Smith said the problem we have with the ES level is that there are about a million designers in the world today, expected to grow to 5 million, which should propel EDA industry growth, however the industry has not had an evangelist educating the market on the importance of making the shift, as it did in previous shifts.
“When we moved to the gate level, the ASIC house saw this as the solution to all their design problems, and went to customers to tell them they had to get off the transistor level and design at the gate level. When we moved to the RT level, two companies specifically – LSI Logic and VLSI Technology – saw this as an opportunity to fill their fabs and subsequently pushed everyone there so they could build 100,000 gate devices instead of the measly 3,000 gate devices,” the Gartner analyst stated.
Smith added that he feels like the “lone wolf crying in forest” and there is not any one company that has a financial stake in it driving the methodology or the adoption of the tools because it’s got to be on the semiconductor companies that are building the systems. Smith believes part of the problem is that many semiconductor companies say they are just building chips, not systems – but in the “S” in “SoC” stands for “system,” and the smart semiconductor company realizes they are no longer in the component business, they are in the systems business. This is why semiconductor companies are going out of business – because they are of the mindset that they are still just building components.
They need to instead determine how much it would cost to build a system if an SoC were not used. Anymore, it’s got to be about the system, he said.
Take Intel for instance. You don’t buy a $5 microprocessor from them, because Intel is building the PC system and they are selling you the heart of that system – the SoC is the heart of that system.
It’s not just about $5 chips anymore – the SoC that drives the market enough to sustain profits will be worth well above $100 – that’s what will drive growth, Smith added.
Another challenge rests in ASIC design starts dropping, with design at 65nm and below posing other dynamics, noted Len Perham, chairman of Optimal Corp., who said he has a real problem with those who say the semiconductor industry is going to grow twice as big in the next four to five years and we are going to do less new products.
“This goes against my 30 years of experience,” he said. “I’m not a big fan of 90nm and 65nm because putting 90nm on 12-inch silicon is very, very complicated and very difficult and very costly in this day and age. And to quote a friend of mine who is a fairly high level guy at TSMC, ‘0.11-micron is going to be around for a very long time.
“If you look at a 0.11-micron chip today, where the power supply is nine-tenths of a volt, and you are building a complicated chip with analog, a lot of logic and memory and you do a timing budget. Nothing that Cadence or Synopsys has will allow you to figure out the signal integrity effects, so there is a real opportunity for EDA companies to innovate,” Perham concluded.
