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Sematech Details High-k Metal Gate Advances
Staff Reporter -- Electronic News, 6/14/2006
During the 2006 Symposium on VLSI Technology being held in Honolulu, Hawaii this week, engineers from R&D organization Sematech shared technical details on metal electrode materials that can be used to build low threshold voltage (Vt) nMOS transistors with high-k dielectric.
Sematech also said it detailed a new approach for creating advanced, low standby power transistors for the 45nm technology generation.
Husam Alshareef, project engineer in Sematech’s Advanced Gate Stack program and a TI assignee outlined the details of the first achievement involving nMOSFETs with metal electrodes showing an effective workfunction of approximately 4.0eV.
This achievement is the highlight of a three-year project involving nearly 40 engineers at Sematech and collaborating universities and suppliers and identifies nMOS metal gate electrode materials, representing a milestone in the quest to fabricate working CMOS devices using metal gate and high-k dielectric stacks through the systematic screening of more than 250 material systems on various dielectrics, Sematech explained in a statement.
“From this work, we developed an understanding of how metal electrode materials and high-k dielectrics react, and how the effective workfunction of metal electrodes can be controlled to yield an effective workfunction close to that of doped polysilicon gates,” said Byoung Hun Lee, manager of Sematech’s Advanced Gate Stack program.
“Our approach will enable the industry to implement metal electrodes with minimum modifications to current CMOS flow,” he added.
In a second presentation, S.C. Song, Material Evaluation Test Structure project manager at Sematech discussed a new approach and processes for creating advanced, low-power transistors that can be used for the 45nm technology generation.
Song described a dual high-k, dual metal gate (DHDMG) process for CMOS field-effect transistors that was demonstrated by Sematech engineers earlier this year that allows several advantages over previously reported dual metal gate integration approaches.
The result is a highly manufacturable flow that can meet industry and ITRS targets for low stand-by power 45nm technology generation, Sematech noted.
“As CMOS devices continue to shrink, SiO2/polysilicon-based transistor structures have become increasingly difficult to scale,” said Raj Jammy, director of Sematech’s Front End Processes Division.
“For the 45nm technology generation, high-k dielectrics and metal gate electrodes have become very attractive, especially for low-power technologies. But until now, there have been no practical approaches to dual metal gate integration,” he explained.
The DHDMG process, developed by engineers in Sematech’s R&D wafer fab ATDF, allows high-k dielectric materials and their associated metal gates to be optimized in separate processing steps, eliminating the difficult integration problems that have plagued more conventional methodologies.
The new process is a flexible scheme that uses two different high-k films if needed along with dual metal electrodes for nMOSFETs and pMOSFETs, respectively to allow nMOSFETs and pMOSFETs to be optimized independently, thus avoiding the deleterious inter-mixing of gate stack materials that typically degrades threshold voltage and other performance characteristics.
DHDMG is also more controllable, resulting in better-defined gate profiles. Ultimately, the process is relatively easy to implement, without the need for additional critical lithography levels or any significant increase in the number of additional steps, the group believes.
“We have demonstrated a manufacturable solution for one of the most vexing problems facing advanced transistor development. The process details have been transferred to Sematech’s member companies for their consideration and we will be working with their engineers on implementation,” Song continued.
Sematech said its progress on both leading-edge nMOSFET metal electrode technology and the novel DHDMG process comes on the heels of last year's related breakthroughs in channel mobility and reliability of high-k metal gate transistors.
