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Automating System Design for Multi-Processor SoCs
By Ann Steffora Mutschler -- Electronic News, 6/23/2006
Although still in stealth mode with a formal launch planned for later this year, executives from Palo Alto, Calif.-based startup Imperas Inc. released a few details on the company’s direction to Electronic News as the Design Automation Conference nears.
The company was founded by Simon Davidmann, who is serving as president and CEO, and brought a wealth of industry knowledge to the company.
Prior to founding Imperas, Davidmann was a VP at Synopsys Inc. following its successful acquisition of Co-Design Automation, the developer of SystemVerilog, that Davidmann also founded.
Before that, Davidmann was an executive with five U.S. based EDA startups including Chronologic which pioneered the compiled code simulator VCS, and Ambit which was acquired by Cadence for $280 million.
After leaving Synopsys in 2003, Davidmann said he spoke to many chip designers and embedded software programmers about what their work. He found that the advanced designers and programmers were starting to face problems when they put multiple processors together in terms of how they were going to develop the chips, optimize them and get the software running on them.
“The thing that struck me is that these advanced designers were starting to have serious challenges and that there are different paths to solving those challenges,” he explained.
“Clearly there is a major change coming. We are at the beginning of a new age, in the same way we were back in the 80’s when we suddenly had ‘seas of gates’ and with the move to ‘seas of processors,’ the software programmers have a lot more challenges. The old ways of doing things just can’t keep going – there needs to be a whole new generation of tools to help these guys,” Davidmann continued.
With this in mind, Davidmann started Imperas to try to ensure that systems get designed and programmed in a very efficient way; that software and hardware can play together and achieve optimal results in the background of multiple processors on a chip.
The landscape for the tools is increasingly complex and costly. “The costs, efforts and risks of building silicon are so high that designers want to get several design wins for each chip,” he said.
“If you talk to camera chip manufacturers for example, they want many design wins for the same chip. So they build a chip which has four or five processors in it, and they want to see it in 20 or 40 different cameras. The differentiation is adding features like simple functionality or advanced functions like panoramic stitching so this one chip can be used in different levels of the market and different markets. In China, the needs for a camera are different than Japan, for instance. In Japan, they want all the functionality; in China, they just want point and click,” Davidmann explained.
Then, “the chip manufacturers want to put in a lot of effort and make the chips right and make them highly programmable and then get lots of design wins. That means the challenge to getting the design wins and the return on the silicon and the royalties is that it has to be easy to get the software onto them, debugged and running efficiently on [the silicon],” he continued.
“They need to understand that as they are building the architecture so as chips get more expensive, they also want to get more design wins and as they get more multi-processor [content], there is more of a challenge on the software. Better solutions are needed to address these issues,” Davidmann asserted as the focus for Imperas.
Funded by Accel Partners and Pond Ventures, the company houses an offshore development group in the U.K. and recently brought on board former Cadence Design Systems executive Frank Schirrmeister as its VP of marketing, based in San Jose, who said the company is, “now in the phase of conditioning the market with respect to what we think the challenges are.”
Prior to joining Imperas, and in addition to Cadence, Schirrmeister held senior management positions at ChipVision Design Systems, AXYS Design Automation (acquired by ARM) and SICAN Microelectronics.
Most recently he served as VP of marketing at ChipVision, a provider of ESL tools for power optimization.
While at Cadence he served as group director of verification marketing in the design and verification business unit and said he was instrumental in shaping the direction of products like the Virtual Component Co-Design Environment and the Verification Cockpit. He also directed the Felix hardware/software Co-Design Initiative and the successful launch of the Cadence Hardware/Software Co-Design and Virtual Component Reuse technology.
During the Design Automation Conference, the company will participate in a technical session on July 26 at 8:30 A.M. in room 306/308 on MPSoC design tools.
During this session in which Davidmann will give a presentation entitled, “System-Level Exploration Tools for MPSoC Designs,” Schirrmeister said the company may “hint at solutions yet to come.”
According to the company’s website, the challenges in designing a modern SoC have stretched the traditional EDA industry to the point that a new generation of technologies are needed to address the ‘above RTL/C’ issues.
Further, the site states Imperas believes that future ICs will not be designed and programmed with the traditional Verilog / VHDL / SystemC ‘write RTL and then write embedded C’ approach, but rather designed and programmed in a unified systems design automation approach where hardware and software issues are combined.
By blending hardware and software technologies and design processes together Imperas aims to provide a development environment for multiple processor SoCs.
