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TSMC Releases 65nm Reference Flow
By Ann Steffora Mutschler -- Electronic News, 7/17/2006
Taiwan Semiconductor Manufacturing Co. (TSMC) today detailed its 65nm Reference Flow 7.0 that contains a statistical timing analyzer (SSTA), new power management techniques along with DFM enhancements since at 65nm, process variations impact timing closure to the extent that new methodologies are needed to predict design performance.
TSMC’s first 65nm reference flow was version 6, released last year. TSMC Reference Flow 7.0 includes a statistical timing analysis capability to optimize design margins and die yields by accurately analyzing the timing effects of manufacturing process variations, the company noted.
Specifically, statistical timing optimizes design margins and die yields by analyzing process variance impact on timing and TSMC’s capabilities include statistical SPICE models, library and IP characterization, standard cell design kits, EDA tool enhancements and corresponding design methodologies.
TSMC believes its Reference Flow 7.0 is the first foundry design methodology to include a statistical timing analysis capability to optimize design margins and die yields by accurately analyzing the timing effects of manufacturing process variations.
Statistical timing analysis tools included are from Cadence Design Systems, Synopsys Inc.’s Galaxy Design Platform technologies and Magma Design Automation’s Quartz SSTA's statistical timing analysis capabilities.
In the area of power, which “continues to be a major consideration in terms of how to quantify dynamic and leakage power,” Ed Wan, senior director of design services product marketing at TSMC explained that at 65nm, leakage power has surpassed dynamic power, “even if the circuit is just sitting there.”
“The less dynamic power used, the more leakage occurs. For every process node, the leakage power doubles,” he noted.
As a result, TSMC built on its power management methodologies from previous reference flows, and has included new tools for dynamic and leakage power reduction
For dynamic power reduction, TSMC has included an enhanced voltage island implementation and multi-corner timing closure, while a coarse-grained power gating technique helps achieve leakage reductions of up to two orders of magnitude, prevent electromigration, minimize voltage drop, and ensure fast wake-up time.
As well, the foundry is offering power management libraries such as isolation cells and data retention flip-flops, along with a new level shifter cell with a 50 percent area savings.
Then, to address DFM issues, TSMC’s Reference Flow 7.0 contains analysis and optimization capabilities to catch potential DFM issues early and can help make needed changes prior to tape-out.
For example, critical area analysis (CAA) identifies random manufacturing defect caused by conducting or non-conducting particles and drives wire spreading and wire widening corrective actions, while virtual chemical mechanical polishing (VCMP) analysis identifies metal and dielectric thickness variation hot spot, and guides dummy metal insertion to improve thickness uniformity throughout the chip. TSMC believes the VCMP timing analysis is the industry’s first DFM timing capability.
Additionally, select lithography process check (LPC) post-production tools have been qualified by TSMC as DFM compliant.
Additionally, in order to help improve production ramps, initial yield, and ROI without compromising on die size or performance, TSMC announced today that Anchor Semiconductor, Cadence Design Systems, Clear Shape Technologies, Magma Design Automation, Mentor Graphics, Ponte Solutions, Predictions Software, and Synopsys have achieved DFM compliance for their 65nm tools with the foundry.
The DFM compliance was achieved through proactive work between TSMC and these EDA vendors to create and qualify interoperability between the foundry’s DFM data sets for advanced technology and the EDA tools and models that designers use, TSMC said.
TSMC’s DFM Unified Format is the foundation for the tool compliance program. The foundry and DFM tool providers have run multiple compliance tests to validate interoperability between the format and tools to ensure that the tools and models that designers use can fully access and utilize TSMC’s process-specific, encrypted DFM Data Kit.
To achieve this compliance, DFM tool accuracy, performance as well as usability all must be verified with massive foundry data, a task that can only be accomplished in collaboration between the foundry and its partners, TSMC concluded.
