EDA Players Detail Involvement in TSMC Reference Flow

Staff Reporter -- Electronic News, 7/18/2006

Following TSMC’s announcement Monday regarding its Reference Flow 7.0, EDA vendors are fleshing out their respective pieces and support of the world’s leading foundry’s recommended flow.

Cadence Design Systems Inc. said today its Encounter digital IC design platform and Allegro system interconnect platform has been integrated into TSMC’s reference flow.

This integration delivers an RTL-to-package reference flow for faster time-to-volume for high-performance designs and low-power designs, via a methodology to address complex design issues at 65nm, such as tight manufacturing parameters, an exponential increase in leakage power, and new extraction requirements.

Within TSMC’s reference flow, Cadence says its technologies address these key issues by improving concurrent routing and dual-via insertion, adding new leakage power reduction strategies, addressing process-variation extraction issues, and optimized package performance and cost.

Also within Reference Flow 7.0, Cadence is for the first time providing a complete RTL-to-GDSII and package flow, including all past and present TSMC Reference Flow capabilities for optimal customer referenceability.

TSMC said it worked closely with Cadence to meet the complex requirements that designers are facing at 65nm such as power management, chip and package co-design, and manufacturing.

Wei-Jin Dai, corporate VP of R&D at Cadence said the breadth of offerings and the capability to integrate into an easy-to-use flow is the key value that Cadence delivers to customers. Cadence also offers a 65LP tutorial and test case in the TSMC Reference Flow. Customers can download and walk through the complete flow with a real design.

In the area of power optimization and analysis, the TSMC Reference Flow 7.0 leverages key elements of the Cadence Encounter platform, including voltage domain-aware technologies used to create power-gated paths and dynamic-voltage scaling, as well as path-specific power optimization using fine grain multi-threshold transistors (MTCMOS). The flow also expands the range of power optimization options to include both coarse grain MTCMOS power gating and dynamic-voltage and frequency scaling.

Complementing the power optimization choices, Cadence said its Encounter platform in Reference Flow 7.0 is meant to allow designers to perform multiple mode/multiple corner timing closure, automatic decoupling capacitor insertion, and dynamic IR analysis, taking into account all power optimization modes.

Elements of the Encounter platform within Reference Flow 7.0 include Encounter RTL Compiler global synthesis, Encounter Test, SoC Encounter system, Cadence QRC Extraction, VoltageStorm Dynamic Gate power rail analysis, and CeltIC Nanometer Delay Calculator (NDC), which work together to deliver high quality of silicon (QoS), improved timing closure, and reduced area.

Then, in the DFM space, Cadence’s SoC Encounter Global Physical Synthesis (GPS) addresses critical manufacturing issues in the IC design process such as wire spreading, double-cut via optimization and metal fill. SoC Encounter GPS can automatically insert metal fill into a placed and routed design to achieve a metal density within the range recommended by TSMC design rules. It also allows automated wire-spreading and double-cut (dual) via insertion, which positively impact yield.

New capabilities in Reference Flow 7.0 include recommended DRC rule routing, half-track wire spreading, and critical area analysis (CAA), which analyzes wire density in a design vs. defect rate/size to derive maximum theoretical yield. SoC Encounter DFY has been certified by TSMC as DFM compliant for CAA.

Further, Cadence’s Allegro platform aims to improve chip/package integration in TSMC Reference Flows such as the new capability of handling simultaneous switching outputs in timing and IR drop analysis. The flow also includes the capabilities to estimate the ratio of signal to power and ground bumps, estimate the number of vias needed on multiple planes in the package and estimate the number of decoupling capacitors needed in the package.

Cadence’s Encounter Test has been validated by TSMC in Reference Flow 7.0 to address at-speed and power-aware ATPG, at speed- and faster-than-at-speed test, and ATPG test compression since at 90nm nanometers and below, test vectors themselves can cause dynamic IR drop issues during test -- indistinguishable at first glance from a failed chip.

Power-aware test allows an understanding of the magnitude and sources of power consumption via toggles in scan flops -- thus permitting both re-architecture of test patterns to avoid problems and allowing scan-flop-specific optimization to reduce power impact. Faster-than-at-speed test allows testing of the design with a throughput higher than the tester clock rate, while ATPG test compression uses on-board logic to reduce the number of pins and tester-applied vectors needed to achieve test coverage.

Finally for Cadence, a new capability in Reference Flow 7.0 and the Encounter platform is statistical static timing analysis (SSTA) which uses a statistical distribution of cell timing/interconnect variance to determine the statistical distribution of timing of paths as would be expected in silicon.

Cadence’s QRC Extraction is used to extract parameterized RC as a function of process variations, meant to improve the performance and accuracy for SSTA. Using the advanced statistical modeling capability of Virtuoso Spectre Circuit Simulator, the process variation information provided by TSMC is accurately simulated and then converted into statistical cell timing models by SignalStorm-LC for statistical timing analysis.

Next, Mountain View, Calif.-based Synopsys Inc. said its Galaxy design and DFM platforms are supported in TSMC's Reference Flow 7.0, which includes Synopsys’ IC Compiler next-generation physical implementation to provide new low-power and yield capabilities that address 65nm design challenges.

Synopsys said the reference flow utilizes key capabilities of Synopsys' Galaxy design platform to address low-power and yield requirements, including concurrent multi-corner/multi-mode optimization for multi-voltage designs and chemical mechanical polishing (CMP)-aware model-based metal fill for optimal results in metal thickness.

From Synopsys in the area of power optimization and analysis, the company said TSMC’s flow includes new low-power design capabilities within Synopsys' Galaxy design platform, including power domain specification and verification at the RTL level, concurrent multi-corner/multi-mode optimization for multi-voltage designs, coarse-grain multi-threshold CMOS (MTCMOS) logic for leakage mitigation, and dynamic voltage-drop analysis considering MTCMOS rush currents.

Synopsys' existing low-power design methodologies such as clock gating, power network synthesis, power-aware placement, low-power clock-tree synthesis, multi-threshold leakage power optimization, and static/dynamic voltage-drop analysis are also included in flow.

Reference Flow 7.0 incorporates a complete Synopsys-based RTL-to-GDSII solution utilizing the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery Verification Platform with VCS and HSPICE for RTL verification and circuit simulation.

As an integral part of the reference flow, extensive Galaxy support includes Design Compiler logic synthesis solution, Power Compiler multi-voltage power management solution, Leda RTL Checker, DFT MAX 1-pass test synthesis solution, Jupiter-XT physical planning solution, IC Compiler physical implementation solutions, PrimeTime and PrimeTime SI static timing and signal integrity sign-off solutions, PrimeRail power network sign-off solution, PrimePower and PrimeTime PX full-chip power analysis solution, Star-RCXT extraction solution, Hercules PVS physical verification solution, and TetraMAX automatic test generation (ATPG) solution.

In addition, Synopsys said its professional services provide expertise in chip implementation and flow deployment services with the TSMC flow.

From Wilsonville, Ore.-based Mentor Graphics Corp., the company‘s entire design for test (DFT) tool suite is included in the TSMC Reference Flow 7.0.

YieldAssist joins TestKompress in the Reference Flow 7.0 in order to allow designers to use a fully verified DFT flow from test generation through failure diagnosis based on Mentor Graphics' tools and methods.

With the addition of YieldAssist to TSMC's Reference Flow 7.0, Mentor said its DFT tools provides an entire flow that offers effective scan testing, test pattern compression, memory built-in self-test (BIST), and failure diagnosis. TSMC provides a complete set of application notes and tutorials to facilitate DFT implementation.

Magma Design Automation Inc. said its tools are also integrated into TSMC’s Reference Flow 7.0 including its IC implementation system that contains Blast Create, Blast Fusion, Blast Power, Quartz SSTA, Blast Yield TX and Quartz DRC, meant to allow designers to address the design challenges and variability that emerge in 65nm process geometries.

With this flow, Magma says designers can achieve better timing, area and power, more robust designs, higher yields and faster time to production silicon.

TSMC has included statistical static timing analysis (SSTA) as well as advanced low-power and design for manufacturability (DFM) methodologies in Reference Flow 7.0. This is the first TSMC reference flow to include the complete Magma methodology.

Finally, Mountain View, Calif.-based Apache Design Solutions RedHawk-LP MTCMOS dynamic verification with advanced power switches, RedHawk-EV modified SDF (MSDF) for full-chip STA timing and PsiWinder critical path timing and clock skew and jitter analyses are used in TSMC’s Reference Flow 7.0.