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CAST Targets Small, Fast Systems with Low-Power, 32-bit Cores
Staff Reporter -- Electronic News, 5/16/2006
Semiconductor intellectual property (IP) provider CAST Inc. today announced the immediate availability of a new line of 32Bit microprocessor cores for the embedded systems market.
The new advanced processing solution (APS) family of cores was developed by French partner Cortus SA as more capable than an 8 or 16Bit processors but with advantages over most 32Bit processors. The APS line is a step up for system designers needing more than an 8051 or 6805 but less than a typical processor from ARM or ARC core.
“We’ve helped hundreds of designers succeed with 8051s and other controllers, and that market’s clearly continuing to grow,” said Hal Barbour, president of CAST in a statement.
“But some systems just need more horsepower. Those designers have had little choice but to live with the technical and business overheads of an advanced 32Bit processor without actually using all its capabilities. Now these APS cores provide an excellent 8/16Bit upgrade solution, and we’re excited to be bringing them to existing and new CAST customers.”
The APS cores use a RISC architecture in a full 32Bit design and have features that make them both a better technical fit and a better IP experience than competing processor cores, CAST believes.
Their advantages include small size, high performance, low-power operation and a development environment.
CAST says APS is more compact than many 8Bit processors, requiring as few as 7,000 gates and easily fitting in many low-cost FPGAs and a wide range of ASICs. It is also faster than the microcontrollers it replaces, benchmarking at 0.6DMIPS/MHz; it operates with very little power, requiring just 18milliwatts per MHz; is supported by a development environment as well as third parties such as MicroCross Inc. and SoC Solutions Inc.
Two APS processors are shipping now, APS2 and APS3.
The APS2 core is a general-purpose processor designed for high-performance, low-power, 32Bit computing. It is optimized for small chip size for a wide variety of applications.
The APS3 core uses the same 32Bit architecture, but is optimized to achieve the most compact programming code for applications sensitive to code density. This makes APS3 especially suitable for encryption, wireless communications, and other systems requiring considerable application code, as well as for hand-held, battery-driven, and other power-critical systems. It uses instructions of 16 and 32Bit length, and interfaces efficiently with 16Bit memories.
Both APS cores are modern RISC designs with a load/store architecture. They feature out-of-order instruction completion, fully-vectored interrupts, a programmable priority interrupt controller, and support for various peripherals and memory interfaces. Their patented co-processor interface makes it easy to extend the instruction set and optimize the processor for any specific application, such as increasing the speed of a digital signal processing algorithm. Barrel shifter and multiplier co-processors are available.
From their inception, CAST says the APS processors were designed for efficient high-level programming using C and C++, and an adapted version of the GNU Compiler Project tool set is included with the cores to facilitate this. Unusually complete, this tool set includes a graphical debugger that connects through a JTAG link or via the serial port on a PC, a comprehensive instruction set simulator, and a standard library of C routines for embedded systems. An APS version of the productivity-enhancing MicroCross development environment will also be available this quarter, through a partnership with that company.
The new cores have been rigorously verified through thousands of test cases and many different applications, and have been successfully implemented in FPGAs from vendors such as Actel and Xilinx. Results with ASIC reference designs show the cores to be highly competitive in terms of speed and area, CAST added.
CAST is shipping the cores now through a straight usage fee or royalty-based licensing model.
