How to Electrically Qualify High-k Gates

As the size of transistors continues to scale down, the use of conventional SiO₂ as a gate dielectric material is approaching physical and electrical limits.^1,2 The principal limitation is high leakage current caused by quantum mechanical tunneling of carriers through the thin gate oxide.³ To reduce gate leakage current, high-k gate materials such as hafnium oxide (HfO₂), zirconium oxide (ZrO₂), alumina (Al₂O₃) and their silicates⁴ have drawn a great deal of attention in recent years. Because of their high dielectric constants, the gate dielectrics can be made much thicker than SiO₂ while achieving the same gate capacitance. The result is lower leakage current — sometimes several orders of magnitude lower.
 
One of the remaining challenges of deploying high-k materials is reliability. This includes phenomena affecting material reliability, such as voltage breakdown and defect generation mechanisms, and phenomena affecting device reliability, such as hot carrier injection and charge trapping. To characterize the reliability of high-k gate materials fully, multiple measurement techniques are typically required. Usually, these techniques include I-V, C-V, charge pumping and other measurements.

Various instruments can be used to take these measurements, but a fully integrated device characterization test system speeds testing and provides a high level of data integrity. These systems typically integrate source-measure units with a C-V meter and a pulse generator to characterize charge-trapping phenomena inside the high-k gate material. They can be used with various charge-trapping measurements, including a relatively new stress and charge-pumping technique that better characterizes traps in high-k films.

Charge-trapping techniques involve a series of voltage stresses of certain duration. During voltage stress, leakage current is measured in real time to calculate the amount of charge injected into the gate. This quantity is expressed as:

Between voltage stresses, three types of measurements can be done in sequence: C-V, I-V and charge pumping. From these measurements, important device parameters can be extracted and plotted as a function of time to show the degradation caused by the stresses.

For instance, in stress and C-V measurements,⁵ the device under test (DUT) usually is a MOS capacitor. A C-V sweep is performed on the DUT before and after voltage stress. The C-V sweep can be a full sweep from inversion to accumulation, so that a flat-band voltage can be calculated by quantum mechanical modeling.

However, a faster and easier way is to do the voltage sweep in a relatively small voltage range around an estimated or predetermined flat-band capacitance. The flat-band voltage is then extracted from the C-V data. Either a single sweep or bidirectional sweep can be used; a bidirectional sweep will show any hysteresis effects associated with the measurement itself.

Flat-band voltage as a function of stress time or injected charge provides information on how much charge is trapped in the gate stack structure. The trapped charge may be characterized by an effective value assumed to be located at the insulator-silicon interface (Q_trap), given by:

Trapped charge calculated from the change in flat-band voltage is an approximation of the charge located in the insulator structure. However, since charge can be generated in places other than at the silicon-insulator interface, stress and C-V measurements only give a rough estimate of how much charge is trapped due to injected charge. Figure 1 shows sample data.

1. Trapped charge calculated from the change in flat-band voltage approximates the charge located in the insulator structure. This screen shot shows a sample plot of trapped charge (Qtrap) and flat-band voltage shift (DFBV) vs. injected charge (Qinj) for a HfO2 film (EOT=1.2 nm).

This measurement technique has the advantage of being simple and direct. It measures the effect of trapped charges from the C-V curve shift along the voltage axis as a function of injected charges. However, it is essential to avoid relaxation of trapped charges during the stress cycle. If trapped charges de-trap too fast, some of the trapped charges may be lost during switching between the stress and C-V measurements. Minimizing the switching time is the key to success in this measurement. Another drawback with C-V is that it measures the combination of traps initially in the film, plus those created later by the stress.

Stress/I-V measurement is similar to stress/C-V measurement, except that a MOS transistor is used as the DUT. During stress, the source, drain and substrate terminals of the MOSFET are grounded; stress is only applied on the gate dielectric. After stress, a V_gs-I_d test is performed, so that key parameters, such as threshold voltage (V_t) and channel transconductance, are extracted. Plotting the shift of those parameters as a function of injected charge makes it possible to obtain the trapped charge density.

This method requires only I-V measurements, so it offers the advantage of being conducted without the need for a switching matrix, avoiding or significantly reducing charge relaxation effects. This is particularly true if stress testing is done under operating polarity, eliminating the need for stress polarity reversal, a major source of detrapping. However, modeling work is required to interpret the data.

2. Applied voltage waveform diagram for stress and C-V/I-V measurement.

Figure 2 is an example of voltage waveforms applied to an MIS capacitor in one stress cycle that includes stress, C-V and I-V measurements. A forward and backward C-V sweep (center waveform in Fig. 2 ) might be used to uncover any hysteresis effect in the high-k dielectric film. The instrumentation must be switched from stress to C-V measurement, so a voltage discontinuity appears at the DUT terminals during the switching time. This voltage discontinuity could result in relaxation of trapped charges from trapping centers. If so, the C-V measurement afterwards would indicate a smaller flat-band voltage shift due to fewer trapped charges. Therefore, the switching time between instruments must be minimized.

Charge-pumping (CP) measurements are widely used to characterize interface state densities in MOSFET devices. This type of measurement is especially useful for thin gate materials that have relatively large gate leakage currents when accurate removal of the gate leakage is done.^6,7 Such leakage makes it difficult, if not impossible, to collect simultaneous quasistatic and high-frequency C-V measurement data needed to estimate interface state densities. The interfacial-trap density within an energy range is calculated by:

where I_cp is the measured charge-pumping current, q is the fundamental electronic charge, A is the area, f is the frequency, and ΔE is the difference between the inversion Fermi level and the accumulation Fermi level.⁸

The basic charge-pumping technique involves the measurement of the substrate current while applying voltage pulses of fixed amplitude, rise time, fall time and frequency to the gate of the transistor with the source, drain and body tied to ground (Fig. 3a ). The application of the pulse can be done with a fixed-amplitude voltage base sweep or with a fixed base variable amplitude sweep.

3. Charge-pumping measurements basically involve the measurement of substrate current while applying voltage pulses to the transistor gate, with the source and drain connected to ground (a). Application of the pulse can be done with a fixed-amplitude voltage base sweep (b), or with a fixed base variable amplitude sweep (c), with energy levels and waveforms shown.

In a voltage base sweep, the amplitude and period (width) of the pulse are fixed while sweeping the pulse base voltage (Fig. 3b ). At each base voltage, body current can be measured and plotted against base voltage (I_CP vs. V_base). The interface trap density (D_it) as a function of band bending can then be extracted from the charge-pumping current if the ΔE is known.

In the variable amplitude sweep, base voltage and pulse frequency are fixed with step changes in voltage amplitude (Fig. 3c ). The information obtained is similar to that extracted from a voltage base sweep but, in this case, I_CP vs. V_peak is plotted. These measurements can also be performed at different frequencies, so that a frequency response of interface traps can be obtained.

For high-k gate stack structures, the CP technique can quantify the trapped charge (N_it) as:

because trapped charge beyond the silicon substrate/interfacial layer can be sensed.⁹ N_it is the trap density measured without determination of ΔE. Figure 4a shows the characteristic N_it curve for the base voltage sweep technique, while Figure 4b shows the N_it characteristic for the fixed based, variable amplitude technique.

4. Examples of charge-pumping measurements on MOSFET with high-k gate materials. A conventional base sweep at different frequencies (top), and amplitude sweep at different frequencies (bottom).

Stress C-V, stress I-V, and charge pumping can provide information about charge centers associated with defects already in a gate dielectric film. However, for stress C-V and stress I-V, it is not possible to distinguish between charge centers initially in the film and those created during a measurement stress cycle. Both types contribute to the shift in flat-band voltage during measurements.

However, a recently developed technique can distinguish the initial charge-trapping centers from those created later in the film by voltage stresses. This technique uses a combination of stress and charge-pumping measurements. A major distinction and advantage of the new technique is that relaxation of trapped charges during the stress cycle will not affect overall measurement accuracy.

The charge-pumping measurements detect traps in high-k gate stacks so, with some modeling work, it is possible to compare results of charge densities before and after a stress cycle. This indicates how many new charge centers were created by injected charges.

5. Stress and charge-pumping measurement on an nMOSFET transistor with an ALD HfO2 gate dielectric and chemical oxide interfacial layer. Result of the stress with interspersed CP measurement after stress (a), and increase of maximum interface trap density as a function of amount of injected charges (b).

Figure 5 shows results from stress charge-pumping measurements on an nMOSFET with W/L=10/1 µm. The gate stack is an ALD HfO₂ with a chemically grown interfacial oxide (EOT of 1.7 nm). ¹⁰ Figure 5a shows a sequence of charge pumping measurements with fixed pulse amplitude. Voltage stresses are applied to the gate between charge-pumping measurements. Figure 5b shows change of maximum N_it extracted from Figure 5a as a function of the amount of injected charge.

The core instrumentation for these measurements is a semiconductor characterization system (SCS) with multiple source-measure units (SMUs) and pre-amps that provide sub-femtoamp resolution for gate leakage currents.

6. Semiconductor characterization system.

This instrumentation is combined with a capacitance-measuring instrument, pulse generator unit (PGU) and semiconductor-switching matrix for a complete measurement solution (Fig. 6). The equipment rack in Figure 6 includes:

• Keithley Model 4200-SCS
• Keithley Model 590 C-V Meter or Agilent Model 4284 LCR Meter
• Agilent 8112 or 8110/81110 PGU (not shown)
• Keithley Models 707A and 708A switching mainframes with Model 7174A ultralow-leakage switch matrix cards (not shown)

The PGU supplies the voltage pulses for charge-pumping measurements. The PGU and C-V meter are connected to the rows of the switch matrix card. DUTs are connected to the columns of the matrix cards. The low leakage and minimal dielectric absorption of the 7174A cards ensure that DUT measurements can be made faster and more accurately than with general-purpose switching cards. The SCS also has dynamic Trigger Link outputs for control of internal and external instrumentation without using the GPIB, which also speeds up measurements. Its prober drivers provide manual and automatic control of on-wafer measurements.

For this hardware, the test application is written for use with the Microsoft Windows NT operating system running on the PC in the SCS. The software provides test definition, automated control, parameter analysis and data graphing. Built-in measurement configurations include a sweep mode with nine forcing functions, which reduces programming requirements. Communications between the CPU mainboard and SMUs takes place over a PCI interface, which is much faster than a GPIB interface, and key to minimizing switching times.

7. Charge-trapping software shows, for instance, the test setup, device setup and charge pumping results.

Figure 7 shows two screen captures of the charge-trapping software interface for a test setup and a charge-pumping data plot. To get a complete picture of charge-trapping phenomena in high-k dielectric materials, it's necessary to configure individual tests for all the plausible combinations of stress, C-V, I-V and charge-pumping measurements. Typical test variables are listed in the Table . Depending on the SCS, data could be stored in text or Excel format for post-processing.