Wafer-Level Advanced Packaging Technology

Despite broad declines in the overall semiconductor market segment in recent years, demand for advanced packaging technology continues to rise. Until recently, much attention was focused on gold bump, solder bump and wafer-level chip-scale packaging. The realization that device performance is limited by package performance is promoting the adoption of innovative packaging technologies. Some of these opportunities include fabrication of I/O redistribution structures, on-chip integrated passives and thick copper traces for power management.¹ While the growth opportunities for these emerging advanced packaging applications are huge, challenges to equipment sets and process parameters loom large during the emergence phase.

There is a growing disparity between the advances in IC technology and device packaging technology. In recent years, packaging interconnect technology has become one of the bottlenecks in productivity, performance, energy dissipation and signal integrity in leading-edge devices. In addition to flip-chip and wafer-level packaging, device manufacturers and foundry suppliers are focusing on innovative methods to increase the performance and decrease the size of a device. Additional wafer processing in the back-end assembly process has been practiced on a limited scale for years to enhance device functionality. The application and complexity of this "post-passivation layer" wafer processing in the back end will increase as innovative technical solutions are required to enable future high-performance devices.

A post-passivation layer (PPL) is defined as any layer or structure above the final passivation of a chip that adds functionality to the semiconductor device. As seen in Figure 1 , these "above-chip" structures typically are formed on a wafer using thin-film dielectrics, along with sputtered and plated metals. PPL processing can be used to integrate a function that could be performed off-chip, but is desirous to include on-chip for form factor or performance reasons. Formation of structures with PPL processing vis-à-vis wafer fab or back-end-of-line (BEOL) processing is advantageous for several reasons: There is no requirement for the fine features achievable with standard mix-and-match lithography; and a wider range of material properties and thicknesses are possible using advanced packaging processes and equipment.

1. Post-passivation layer (PPL) structure on silicon device where many new packaging technologies extend chip functionality. Note: Drawing not to scale

The use of PPL processing for enhancing device functionality is expected to grow significantly in the next several years. Applications run from established technologies currently in production to those that will be required to enable leading-edge products. The potential application of organic and metal layers to create functional structures on a chip in wafer form is endless. However, in the near term, future product requirements will drive a few key growth areas for PPL — redistribution, above-chip passives, thick copper for power, and stress buffer layers. In each case, similar structures can be formed in wafer fab or BEOL, but the use of PPL processing allows different materials and material thicknesses (albeit at grosser geometries) to be used.

One current and well-known use of PPL structures is the formation of redistribution layers on a chip. The bond pads of a device, typically designed for a wire-bonded interconnect, are routinely rerouted to more favorable locations on the surface of the chip using a passivating organic layer (e.g., polyimide (PI) or benzocyclobutene (BCB)), a layer of patterned metal (e.g., copper), and another layer of organic passivation on top for protection.

Redistribution is often used to move peripheral bond pads on a tight pitch to a more relaxed pitch in an array for flip-chip mounting or wafer-level packaging. In addition, redistribution is finding increasing use in stacked-die packages where rearrangement of I/O is required to wire bond complicated nets. For a large number of die vertically stacked in one package, or for die with unusually large numbers of I/O, bond pads are not always in the place where they are most easily interconnected.

The need to integrate passive components in wireless devices is easily understood when one considers the >500 million units of cellular phones that are expected to ship worldwide in 2006,² and the large contribution that passive components make to a system's cost, size and weight.³ There is an array of integration choices available for reducing the volume and cost of passives in a system, including integrated passive devices (IPDs), embedded passives in substrates, and on-chip passives fabricated in the IC.⁴

Fabrication of above-chip passives using PPL processing allows designers to take advantage of thick dielectric layers for capacitors and thick copper for inductors. Process technologies and an infrastructure to support PPL passives are still in development. As there are a number of viable passive integration technologies available, the selection of one is complex and involves careful consideration of cost and performance trade-offs.

A related structure is a high-performance PPL transmission line using thick dielectric materials and ground planes. The need for this type of structure is being driven by increasing device speed and data transmission rates. Off-chip solutions have been proposed, but these are unlikely to develop, as they would likely make the device untestable. By implementing the transmission line in a dielectric and wiring layers above the IC, the same result can be achieved, and the device remains testable and, more importantly, under control of the IC fab.

Certain devices require thick copper on the surface of the die to carry high current. This is especially true for intelligent power devices that integrate logic and power on a single chip for automotive, inkjet print head and other applications. The required 5-10 µm of copper for these applications is generally not achievable in front-end operations, but rather must be done post-passivation, with plating.

The use of SiO₂ dielectrics has presented no fundamental problems in the implementation of advanced packaging. However, the current introduction of low-k and future utilization of ultralow-k interlayer dielectrics (ILDs) has made the management of stress imposed on the device by the package a critical issue.

2. Solder bump stress failures appear more often in packaging processes that employ porous ultralow-k dielectric systems. (Source: Flip Chip Technologies)

Because of their porous nature, low-k ILDs have shown susceptibility to delamination and cracking in packaging processes such as backgrinding, dicing, wire bonding and flip-chip bumping.⁵ As the mechanical properties of an ILD degrade with increasing porosity, the packaging of ultralow-k ILDs is expected to be even more problematic. Figure 2 shows a typical stress failure of a solder bump on an ultralow-k ILD. Indeed, a chief technologist at a major device maker noted that, although 90 nm devices with low-k ILDs were being packaged satisfactorily, he was "terrified" at the prospect of having to package 65 nm devices with ultralow-k ILDs.

A solution is required to mitigate the stress that packaging will place on these leading-edge dielectrics. The thick, organic PPL structure proposed as a means of protecting ILDs is difficult to implement in standard front-end wafer processing. This type of PPL structure is not currently in production to protect ultralow-k dielectrics, but development of materials and processes is underway.

Advanced packaging techniques continue to gain mainstream acceptance. Post-passivation lithography techniques are being used to enhance device functionality. While these technologies hold significant promise, it is extremely important to pay considerable attention to the equipment used for various process steps.

As flip-chip and wafer-level packaging techniques achieve industry acceptance, device manufacturers are faced with several manufacturing challenges. To address the technology needs, they are applying traditional front-end lithography equipment to leading-edge back-end packaging applications. This adoption has also been accelerated by the realization that the imaging requirements of wafer bumping are subject to the same production necessities as front-end semiconductor fabrication.