Thermal Processing Tackles New Processes, Materials

The industry is in a setting where nanometer-scale movement of dopant profiles significantly influences devices. This requires that dopant diffusion and activation phenomena be understood to an unprecedented degree, which includes matters such as activation limits and thermal budget reduction requirements.
 
"Changes are coming to the gate stack, the substrate area, and in junction definition," said Randhir Thakur, vice president and general manager of the Front End Products Group at Applied Materials (Santa Clara, Calif.). "In each there are new materials, new processes, new product development, or new architectures. If a combination of these — the strained silicon, elevated source, along with the oxynitride — can drive that 17% year-over-year performance improvement, we can delay the need for high-k. Time is of the essence, and chipmakers don't have the time required to look at these new materials and capabilities, bring them in, go through the learning curve, integrate them appropriately, then roll out a chip and hit the market window." (Fig. 1 )

Jeff Hebb, RTP process technology manager for Axcelis Technologies (Beverly, Mass.), sees two important RTP trends. "One is in silicidation. As we go from 130 to 90 and then to 65 nm, we're seeing a cobalt-to-nickel migration. Most everyone agrees nickel is necessary at 65 nm, with some looking at the latter stages of 90 nm for high-performance devices."

Paul Timans, director of technology for the RTP Products Business Unit of Mattson Technology (Fremont, Calif.), predicts a continued expansion of RTP applications, driven by thermal budget reductions. "Now that we're well into the nanometer world, more precise control of dopant diffusion in device structures is essential because even very small movements in the doping profiles affect device performance," he said. "Another area where RTP will be especially important is in the minimization of parasitic resistance and capacitance through optimized annealing processes and thermal activation of implanted dopants in new materials, including strained silicon and SOI."

"If we consider the transistor and what surrounds its architecture, a few things stand out," Thakur said. "One is the basic gate stack, where we've had conventional oxide, which we could scale down without major changes, obtaining a 17% yearly improvement in the transistor's basic performance. Now we're bringing in new materials — nitridized oxides — but the dielectric still is amorphous and the base oxide remains." This change is in progress. Logic adopted it at 130 nm, and others for design-level changes, where mask levels can be reduced and benefits on refresh times for memory obtained. Meanwhile, the electrode poly remains unchanged.

1. With increasing demands on process characterization and speed, plus the introduction of complex, increasingly smaller architectures as well as exotic new materials, thermal processing technology faces a number of challenges, some of which can be postponed through workarounds. However, the approach of fundamental physical limits will require hard choices. (Source: Applied Materials)

The conventional oxide with the standard doped — sometimes implanted — poly, transitioned into silicide, then to oxynitride. The key was to bring in an in situ heavily doped poly for less depletion and continued scaling. "At 65 nm, this introduces the question of high-k," Thakur said. "Here, instead of poly, chipmakers will consider metal gates — already being discussed by logic providers — and highly doped electrodes. On the gate stack side, metal gate becomes an obvious option."

Another critical change starting at 65 nm is in the silicon substrate. "We had epitaxial wafers, bulk epi, and considered elevated source/drain for the insertion of a new capability in epi: selective process," Thakur said. "For the last two decades selective process — selective tungsten, selective FSGs — never happened. But selective epi for elevated source/drain, as well as in the DRAM area, is real. Because conventional epi is mature, you can incorporate germanium and improve drive current."

Logic looks at SOI. Regardless of the SOI technology (SiMOSFET, layer transfer, etc.), SOI will provide power dissipation benefits for logic. For device makers to adopt it, it must be low-cost and high-performance. However, change in some areas is inevitable as engineers run out of workarounds. SOI may or may not be used at 45 nm, but at 32 nm it's considered a certainty, Thakur said. "The question is junction tailoring, because junctions have become ultrashallow, and channel-related issues show up with shunt devices at 65 nm. First comes the junction implant, then its definition, and it cannot tolerate past thermal budgets. This results in changes in the types of usable species, because higher conductivity is required from this limited junction." For junction definition, conventional methods such as RTP will be tested further perhaps with laser applications, or some new spike anneal method, to cope with thermal tailoring and reduced thermal budgets.

Bob Soave, strategic technologist at Tokyo Electron Ltd. (TEL, Austin, Texas), points out that, for almost a decade, there has been talk about advanced gate stacks. "This is driven by the concern that SiO₂ layers are becoming increasingly thinner because of scaling, resulting in electrical ramifications. Prophets of doom predicted that SiO₂ would be unusable beyond the 0.18 µm node. However, it's been extended beyond anyone's wildest expectations and will probably continue for a while. Nevertheless, we are physically running out of materials to scale, and other dielectric and electrode materials will be needed to replace SiO₂."

These materials will probably be produced by thermal reaction and new chemistries — not as simple as oxidizing silicon or letting silane fall apart to make poly. "Because the chemistries are complex and relatively unknown," Soave said, "the challenge is understanding how the process affects film composition and electrical properties, and developing reactors to work repeatably in a manufacturing environment and integrating everything for the production line."

Michael Grant, vice president of TEL's Thermal Processing Systems Business Unit, sees major issues when considering high-k dielectric with a metal gate. "One is the basic materials and science behind getting them together and deciding which will be used, then there are integration issues. Two years ago, if you'd asked U.S. major logic manufacturers about their gate strategy for the 65 nm node (which lies two years hence) they'd all have predicted that they'd be rolling out their pilot production of high-k dielectric with a metal gate. Now, they're saying probably at the tail end of 65 nm, most likely at 45 nm — and there still are many integration-related questions."

Device makers may be on the SiO₂ gate's last legs. "Some run base oxides in the 8-10 Å range, with special treatment on the oxide," Grant said. "There are leakage penalties to pay at those levels, even with special treatments like nitridation or in some cases a CVD-type nitride application to the base oxide. At an 8 Å base oxide level, the downside may be greater than the benefit."

For leading-edge devices, there is a leakage current, power density issue. "Scaling is helped by voltage drops," said Tony Dip, thermal processing systems process manager for TEL. "But with some of the high-end chips hitting the markets now, you're talking >100 W on a die maybe >1 in.², probably closer to 0.52 and shrinking. I don't know whether anyone who makes chips cares what goes in, as long as the product has the right speed and drive current specs. So on one hand you have drive current and on the other leakage — how do you balance them? Integration is one way; material changes is another. The chipmaker will adopt whichever is the easier."

There are material changes like high-k dielectrics and metal gates, which apparently will go hand in hand — some think that it will be impossible to get a functional solution without both. "The problem is that the technology doesn't work," Dip said. "High-k has complicated electrical responses on silicon, and a thin dielectric reduces MOSFET channel mobility. Thus, going to a thinner dielectric or a higher-k dielectric may not be feasible. If you build to cut leakage currents you must crank the power to get drive currents to where they must be. This cancels much of the high-k dielectric's advantage." High-k remains a remote possibility. Because the fundamentals are not here today, it is increasingly unlikely that high-k will become the technology of the future. Some leading-edge IDMs are going to strained layer technology via novel approaches. All their transistors today involve an oxynitride stack for the gate dielectric, and they are going to squeeze a little more by going to a strained layer — no high-k.

Soave thinks that high-k will come. "It'll be later, probably around the first 45 nm generation. The word 'scaling' has acquired a life of its own. Historically, you don't scale geometries or dimensions; you scale performance. The mechanism was scaling dimensions, geometries. The era of increasing performance solely through geometrical scaling has essentially ended. Other methods will sustain performance improvements — clever design, SOI, strained layer, 3-D devices (each with its own problems). With thermal processing, we'll see continued improvements of existing conventional materials through reactor development and refinement, to make them better controlled, more flexible, lower thermal budget compatible, cost-effective, and more suitable to advance device integrations."

Mattson has focused on a couple of RTP technologies — particularly ultrashallow junction (USJ) formation. "We need very shallow junctions with high activation levels," Timans said. "And today's technology of choice is the high-temperature spike anneal, which gives a maximum activation of dopant with minimum diffusion, and good defect annealing characteristics for quality junctions with low leakage. This process will remain important well into 65 nm — it ensures high activation levels, while minimizing diffusion. At advanced device nodes this trade-off gets increasingly difficult." Advanced devices — certainly logic — will be made with NiSi technology. However, NiSi brings complications, especially the need for low-temperature control in RTP tools.

The question with NiSi is which process is optimum. Nickel processes require lower temperatures than cobalt, so temperature measurement and control become of considerable interest in extending RTP's range. "Our users would like to keep the silicide in the RTP toolset," said Axcelis' Hebb, "but need low-temperature measurement and control. And for the flexibility to explore the process base, the trend is toward RTP pyrometry control in the 250°C range."

Because emitted radiation drops exponentially as temperature declines, a wafer does not emit much energy at these temperatures, and there are difficulties in using pyrometry for measurement and control. "Stray light is another problem. Heating source light reaches the pyrometer, while what one wants to measure instead is the wafer's emitted radiation or light." The hotter the source, the worse the stray light.

A hot wall instead of a heat lamp system can help. "We've shipped systems with 250°C capability, for NiSi development," Hebb said. "Users face one-step, instead of two-step, annealing for NiSi. Cobalt has always been a two-step process; in theory, nickel could proceed with one step. However, there are advantages to the two-step process. We've seen positive results with the two-step anneal, the first step at <300°C."

For Ernst Granneman, business unit manager of RTP at ASM International (Phoenix), a serious thermal processing problem is that more than 90% of RTP systems are lamp-based. "With these systems, the most critical problem is temperature control, reliability, throughput, cost of consumables, and lack of low-temperature capability." Granneman added that conductive heating instead of radiation is a way to solve those issues.

The roadmap for USJ formation includes implant spike anneal and solid-phase epitaxial regrowth, and for junction contacts it foresees transition from CoSi₂ to NiSi. As Granneman puts it, "The processes in the roadmap require extreme capabilities from RTP tools: heat-up and cool-down rates of hundreds of degrees per second, no pattern/emissivity dependence, precise temperature control, and low-temperature (starting at 200°C) operation for NiSi formation. We believe that the way to go is an RTP system based on conduction rather than radiation, to enable continuity in USJ development for current and future technology nodes. It can provide ramp rates in the 300-900°C/sec range, and operate in a temperature range of 100-1100°C with precise temperature control."

To Yasuo Kunii, general manager of the Technology Development Center, Toyama Works, Hitachi Kokusai Electric (Toyama, Japan), the thermal budget is a major processing problem, which he thinks can be solved by new chemicals and plasma processes. "As technology nodes proceed from 130 nm to 45 nm, the thermal budget becomes a serious problem," he said, adding that, for the CVD process, the thermal budget can be decreased by precursor changes. "For example, SiN films are deposited with SiH₂ Cl₂ and NH₃ precursors at 700°C. Changing this from SiH₂ Cl₂ to BTBAS (Bis(TertiaryButylAmino)Silane), enables SiN films to be deposited at 600°C or below, significantly reducing thermal budgets. Changing to batch ALD (plasma processing) for SiN films provides for even lower deposition temperatures of 500°C or below." (Fig. 2 )

2. Thermal budget trends for silicon nitride are becoming increasingly demanding. By the 65 — certainly the 45 nm — technology node, new technologies will become necessary to meet processing and production demands. (Source: Hitachi Kokusai)

Laser processing

Sandeep Mehta, director of strategic applications and process development at Varian Semiconductor Equipment Associates (VSEA, Gloucester, Mass.), views silicidation as the most commonly and widely used step in RTP. "For the past few device generations, RTP has been used extensively for activation of source/drain and extension implants," he said. "Demands for low thermal budgets have resulted in the move away from the traditional furnace annealing to RTP. This trend has progressed to further lowering of thermal budgets with spike anneals involving fast heat-up and cool-down rates."

With the need to go to increasingly shallower junctions, it was felt that traditional spike annealing would become a technology of the past. A few years ago, laser annealing was considered as the best solution for shallow junction formation. "The benefit of laser anneal stems from the fact that it's a zero thermal mass process, meaning there are no filaments, which allows you to raise the temperature rapidly, high enough to melt silicon, allowing for high activated fractions," Mehta said. "However, there are critical integration roadblocks from the standpoint of high-volume manufacturing. From a technical standpoint, there are leakage and residual defect issues that affect transistor performance. Al-though there's still considerable work proceeding in this area, integration of laser processing for USJs isn't considered feasible. In addition, people are pushing implanters to their limits to increase productivity. Thermal processing which follows the implant step must keep pace with these increased productivity requirements."

Dynamic surface annealing is also being tried. This is a sub-melt laser process, working below silicon's melting point — which then becomes an advanced spike anneal. Flash anneal, an extension of the RTP spike anneal, is another option. In this process, the wafer is brought to an intermediate temperature, 600-800°C, then zapped with high-intensity radiation with a very short-duration pulse, which raises the wafer's temperature to the desired level. The radiation is immediately turned off as soon as the peak temperature is reached.

"There is considerable activity to investigate the feasibility of the flash process, and we have seen instances where people still complain about defects and lack of adequate dopant activation," Mehta said. "No one has integrated laser thermal processing for USJs, and the same is true for flash anneal, despite the fact that there is a lot of activity in both areas. The spike RTP process to date is the only manufacturable solution in hand right now."

Device manufacturers will have to come up with an alternative on their own front; whether it is some change in device structure, materials, dopant species, or all of the above to engineer the junction characteristics to sustain the required transistor performance.