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Effective Pore Sealing of Ultralow-k Dielectrics

Christopher Jezewski and William A. Lanford, University at Albany, New York; Christopher J. Wiegand, Jay J. Senkevich and Toh-Ming Lu, Rensselaer Polytechnic Institute, Troy, N.Y. -- Semiconductor International, 5/1/2004

At a Glance
A polymer sealant deposited by CVD demonstrates compatibility with porous MSQ low-k dielectrics, and results in negligible changes in effective dielectric constant. The sealant, poly(p-xylylene), proved impervious to copper precursor during CVD. It is proposed that the sealant has the added benefit of increasing fracture toughness, which would improve the interconnect stack's ability to withstand CMP and packaging processes.

Significant attention is being paid to interconnect material strategies in order to continue to follow Moore's Law. Dielectric materials with effective k values less than 2.5 are expected for sub-65 nm nodes. Extension of existing material strategies is generally preferable to radical changes. One way to extend any class of low-k material (and thus to hold the philosophy of incremental changes) is to make the interlayer dielectric (ILD) porous.

However, the introduction of porosity results in several undesirable properties such as reduced mechanical strength, difficulty withstanding chemical mechanical polishing, failures in packaging, and metallization challenges (due to surface roughness and penetration of precursor gases).

In this article, we discuss some of the problems associated with metallization via chemical vapor or atomic layer deposited barriers/seeds. We show the results of integrating a pore sealant that prevents copper precursor penetration during CVD.

Several authors recently have shown either theoretically or experimentally that porosity can have an adverse effect on the ability to deposit films by CVD.1-3 Namely, the gaseous precursors used in the process penetrate into the film rather than depositing at the surface. Many current capping/sealing strategies for porous materials are described in a recent review.4 In addition, this magazine recently described a new method where porosity is introduced only after full barrier layer and copper metallization.5 In that work, a 100 Å TaN PVD barrier was needed to seal the porous dielectric, given the amount of interconnected porosity (3%) present throughout the preformed solid/porogen dielectric. ALD barriers are fundamentally incompatible with even small amounts of open/interconnected porosity.

Pore penetration

Metallization of nanoporous methyl silsesquioxane (MSQ) via copper CVD (CuII (tmhd)2 and H2 at 217ºC) results in penetration and accumulation of copper at the interface between the dielectric layer and the substrate.3 This result has been investigated by both Rutherford backscattering spectrometry (RBS) and scanning electron microscopy (SEM). Figure 1 shows bare porous MSQ (1a), after 30 minutes of deposition (1b), and after 90 minutes of deposition (1c). Because SEM can only resolve several nanometers of thickness, and because RBS can detect monolayer levels and is also quantitative, we performed RBS for the same sample shown in Figure 1b, with a deposited copper layer of ~190 Å (Fig. 2 ). This figure also shows a spectrum of a partially sealed MSQ sample, where the deposited copper equivalent thickness is only 2.3 Å, too thin to be detected with a SEM.

1. Porous MSQ before copper CVD (a), after 30 min (b) and 90 min of CVD (c). The copper penetrates the film and deposits at the MSQ/substrate interface.

2. RBS spectra showing penetration of deposited copper into bare MSQ/ SiO2/Si (blue), and 11 Å thick poly(p-xylylene)/ MSQ/SiO2/Si (rust). The double arrows show the thickness of the MSQ film as determined by the width of the silicon signal in MSQ. The double arrow represents thickness of MSQ as determined by RBS. Note: The copper peak appears at the interface depth.

Sealing of porous MSQ was achieved by depositing thin films of poly(p-xylylene). Briefly, the precursor [2.2] paracyclophane is sublimed at a temperature of 155°C, then flowed into a high-temperature region (650°C) of the reactor inlet, where it is cleaved into long-lived reactive intermediates by vapor phase pyrolysis. The reactive intermediates are then transported to a room-temperature deposition chamber, where physisorption and subsequent free-radical addition polymerization take place. The process is self-initiated, which results in highly pure, ultrathin films (10-50 Å) that have low molecular weight and are more oligomeric than polymeric.

A poly(p-xylylene) sealant is envisioned to be integrated into the dual-damascene architecture, post-RIE of the hardmask and ultralow-k (ULK) dielectric, and prior to barrier seed deposition. Hardmask, ULK dielectric, and copper at the via bottom are all exposed to the p-xylylene reactive intermediate. There is no growth on the via bottom of the pore sealant (Fig. 3 ). This, fortunately, alleviates the need to clean the via post-sealant deposition.

3. Trench-first integration of poly(p-xylylene) into copper dual-damascene architecture.

Vaeth et al.6 showed inhibited polymer deposition on a copper surface. For example, air-exposed patterned copper on a silicon substrate was tested for selectivity. Profilometry results showed that 335 nm of polymer deposited on the silicon surface without any deposition on the air-exposed copper. Work at Rensselaer extended Vaeth et al. findings using more surface-sensitive techniques.7 X-ray photoelectron spectroscopy and variable-angle spectroscopic ellipsometry were used to characterize and determine the extent of deposition on copper and dielectric surfaces. Selectivity of the copper surface was shown even with native oxide and adventitious carbon layers.

These observations are very promising for the poly(p-xylylene) process in that there are no stringent requirements for preparing the copper surface prior to pore sealing ULK materials. Selectivity in CVD processes is particularly attractive in this application because the reduction of via contact resistance is critical to the performance of future CMOS devices. What's more, ultrathin films (<50 Å) can be easily damaged if the via bottom has to be cleaned.

Ultrathin films of poly(p-xylylene) were deposited onto porous-MSQ then subjected to copper CVD. Figure 4 shows the amount of copper deposited as a function of poly(p-xylylene) thickness. As shown, a sealant film thickness of only 35 Å is needed to reduce the precursor penetration and subsequent copper deposition to below the RBS detection limits. Given the average pore size of 15 Å, with a pore size distribution of 5-40 Å, this sealant film thickness seems reasonable.

4. RBS is used to determine the amount of copper deposited in poly(p-xylylene)/MSQ/SiO2/Si as a function of poly(p-xylylene) thickness. Two data sets, circles and triangles, are from experiments before and after reactor alterations, respectively.9

Sealant effect on keff

Some penetration of the pore sealant into the dielectric is expected but, for poly(p-xylylene), controllable. However, how does the penetration of the pore sealant affect the effective dielectric constant (keff)? Metal-insulator-semiconductor (MIS) capacitance measurements showed that the dielectric constant of the porous-MSQ 5400 Å film covered with 37 Å of the polymer sealant was unchanged. The keff of the low-k stack was calculated from the slope of the measured total capacitance vs. metal electrode area. The measured dielectric constant of porous-MSQ was 2.26, which increased to 2.30 after poly(p-xylylene) anneal at 250°C.

The ~1.7% increase in k was less than the sample-to-sample variation. This minimal change is perhaps expected since the porous-MSQ dielectric was fairly thick. However, it's important to estimate keff for films with technological dimensions. A depth profiling technique was used with a resolution of ~1000 Å to determine whether the sealant penetrated the MSQ. 12C exhibits a strong (α,α) elastic scattering resonance in the energy region of 5.5-5.8 MeV. In this energy region, the cross section is >100× the Rutherford cross section. The resonance is sufficiently broad to enable depth profiling microns deep.

Figure 5 shows carbon depth profiles using the 5.75 MeV resonance. Qualitatively, it can be seen that there is more carbon in the poly(p-xylylene) sealed porous-MSQ. What's more, this extra carbon exhibits an exponential penetration into the dielectric. Any increase in keff is determined solely by the amount of penetrated polymer. Attributing the increased carbon observed in the resonant backscattering to poly(p-xylylene) allows one to estimate keff.

5. Cumulative increase in dielectric constant (top) for increasing film thickness determined from depth profile composition (bottom). Middle: RBS of bare MSQ (rust), poly(p-xylylene)/MSQ (dark blue), and simulation of poly(p-xylylene)/MSQ (light blue). Resulting composition depth profile for the sealed MSQ (bottom).

The lower half of Figure 5 shows the approximate composition of the sealed dielectric as a function of depth. Films used in this study contained 50% porosity; therefore, rust represents the MSQ matrix and white represents the porosity. Initially, the film is composed of 50% MSQ and 50% pores. The polymer is represented by blue. An upper bound of keff is determined by adding the components in parallel within a layer and in series between layers. The top portion of Figure 5 shows the cumulative keff as a function of depth. Resonant depth profiling results were consistent with MIS capacitance measurements of the entire film stack.

Interface fracture toughness

A polymer sealant has the additional benefit of improving interface fracture toughness. It is unknown whether such thin films (<50 Å) will exhibit significant plasticity during interfacial fracture. However, work by Iacopi et al. has shown that a thin (100 Å) organic polyarylene-based hard mask (JSR's FF-O2) resulted in an almost threefold increase in the strain energy release rate, where the failure was induced at the porous-MSQ/FF-O2 interface.8

While no measurements with thin poly(p-xylylene) have been made as of yet, carbon depth profiling revealed an exponential profile of penetrated polymer into the porous MSQ. The very top pores are expected to be filled/sealed as evidenced by the prevention of CVD copper precursor penetration.9 At greater depths, successively less filling is seen over the next 1000-2000 Å. Each pore is coated with the CVD polymer.

Compared with bare MSQ, the debond tip of a propagating crack would be passing through what amounts to a nano-laminate of brittle MSQ and the coated polymer. This thin conformal coating would have an effect similar to an extremely rough interface, and could be sufficient to cause large changes in the crack propagation direction and significant increases in debonded area. The polymer would also interfere with transport of water to the debond tip. Moist environments are known to have significant effects on stress corrosion cracking.10

All of these energy-absorbing processes would contribute to an increase in interface fracture toughness, which in turn allows for CMP and packaging survival, providing there is good adhesion to the metal line. We are currently investigating polymer derivatives that will possess excellent chemical adhesion to subsequent barrier layer or copper metallization.

Summary

A chemical vapor deposited poly(p-xylylene) sealant 35 Å thick was deposited at room temperature onto porous-MSQ. It was shown to prevent copper precursor penetration during CVD. The small amount of sealant penetration into the porous dielectric resulted in a negligible increase in dielectric constant as determined by capacitance measurements and carbon depth profiling.

The sealant is a selective CVD process, and will not deposit on the bottom of the copper via. Selective deposition is a necessary prerequisite for any pore sealing technology. Finally, this polymer sealant may increase resistance to metal/polymer/ULK interface fracture, allowing for greater CMP and packaging reliability.


Author Information
Christopher J. Jezewski is currently completing his PhD. degree at University at Albany . His research interests include plasma assisted copper ALD, high-resolution Rutherford backscattering with near nanometer resolution and ultrathin poly (p-xylylene) films as liners for porous ultralow-k dielectrics. E-mail: jezewc@rpi.edu.
William A. Lanford, E-mail: lanford@albany.edu
Christopher J. Wiegand, E-mail: wiegac@rpi.edu
Jay J. Senkevich, E-mail: senkej@rpi.edu
Toh-Ming Lu, E-mail: lut@rpi.edu


References
  1. M.E. Thomas, D.M. Smith, S. Wallace and N. Iwamoto, "Transport Considerations in Porous Low k and Metal Interconnect Systems Approaching Atomic Dimensions,"Proc. IITC, p. 223 (2002).
  2. W. Besling, et al., "Atomic Layer Deposition of Barriers for Interconnect," Proc. IITC, p. 288 (2002).
  3. C. Jezewski, et al., "Copper Penetration Into Porous Ultra-low-k Methyl Silsesquioxane During Selective CVD," Chemical Vapor Deposition, December 2003, p. 305.
  4. K. Maex, et al., "Low Dielectric Constant Materials for Microelectronics," Journal of Applied Physics, June 1, 2003, p. 8793.
  5. J.M. Calvert and M.K. Gallagher, "A New Approach to Ultralow-k Dielectrics ," Semiconductor International, November 2003.
  6. K.M. Vaeth and K.F. Jensen, "Transition Metals for Selective Chemical Vapor Deposition of Parylene-Based Polymers," Chemistry of Materials, May 2000, p. 1305.
  7. J.J. Senkevich, C.J. Wiegand, G.R. Yang and T.M. Lu, "Selective Deposition of Ultra-Thin Parylene-N Film on Dielectrics versus Copper Surfaces," in press, Chemical Vapor Deposition.
  8. F. Iacopi, et al., "Impact of LKD5109 Low-k to Cap/Liner Interfaces in Single Damascene Process and Performance," Microelectronic Engineering, November 2003, p. 293.
  9. C. Jezewski, et al., "Molecular Caulking: A Pore Sealing Chemical Vapor Deposited Polymer for Ultra-Low-k Dielectrics," submitted to Journal of the Electrochemical Society.
  10. M. Lane, "Interface Fracture," Annual. Reviews of Materials Research, Vol. 33, p. 29 (2003).

Acknowledgements
The authors wish to acknowledge the contributions of Anupama Mallikarjunan (IBM), Dexian Ye, Deli Liu and Gwo-Ching Wang (Rensselaer), and Chanming Jin (Texas Instruments) for their help in preparing this manuscript. We also acknowledge the financial support of NSF and the SRC Center for Advanced Interconnect Systems and Technologies (CAIST).

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