2004 Top Fab: Chartered Silicon Partners

Semiconductor International's annual Top Fab Award was established to recognize outstanding semiconductor manufacturing facilities. We base our decision on several factors, including manufacturing capability, ramp time for new processes, the degree of automation, contamination control procedures, and consideration given to worker and environmental health and safety concerns.
 
This year, the award goes to Chartered Semiconductor Manufacturing's Fab 6, also known as Chartered Silicon Partners Pte. Ltd. (CSP, a joint venture with Agilent Technologies, EDB Investments and Singapex Investments). Nestled along the northern edge of Singapore Island and looking across the serene Johor strait, CSP produced its first production wafers a few days into the new millennium. It has since proven capable of delivering a wide variety of processes and transferred technology; in both aluminum and copper interconnect, from 180 nm through 130 nm technology nodes.

CSP began its track record on a 180 nm aluminum embedded SRAM technology transferred from an IDM seeking to outsource its manufacturing. During the cleanroom construction phase, 12 CSP engineers relocated to the IDM company to collect process information, which was used for recipe creation, equipment matching and for execution of the first lots. A clear indication of the effectiveness of the startup was that, from the date of delivery of the first lithography tool, the first fully processed, yielding wafers were completed in a record 84 days. Equally impressive: CSP's second lot exceeded the best yield achieved up to that point at the transferring fab.

As a result of this success, during the first quarter of 2000, CSP began a similar transfer on a copper process (58 days from wafer start to yielding silicon), making CSP the first copper fab in Southeast Asia. CSP went on to qualify a total of five technology nodes and another six process variants, most of which have been ramped into production. In addition, CSP has been the hosting fab for Chartered's 130 nm node, currently in production, as well as initial 90 nm development prior to the formation of the joint-development alliance with IBM.

Nestled along the northern edge of Singapore Island and looking across the serene Johor strait, Chartered’s Fab 6 produced its first production wafers a few days into the new millennium.

Zadig Lam, CSP's general manager, said the fab has several attributes that have enabled high flexibility and speed:

• CSP is part of Chartered and physically connected to Chartered's three other world-class Fabs 2, 3 and 5 on the same campus. This has allowed CSP to draw from a sizeable pool of technology, engineering and manufacturing expertise. In addition, it has ready access to centralized support functions such as failure analysis capability, CIM expertise, information technology and supply management.
• CSP is a full scanner fab, which allows maximum flexibility and extendibility across technologies.
• The fab leverages bridging tools to support a scaleable technology development roadmap.
• It has in place robust manufacturing systems that have enabled rapid introduction of multiple technologies.
• CSP has an empowered and motivated workforce that is responsive to the challenging environment.

"These and other factors have enabled us to operate our fab with unmatched flexibility from inception to volume production and continuing capacity expansion, while benefiting from productivity gains at the same time," Lam said.

CSP started with 1000-wafer capacity, and ramped to 18,700 per quarter by the end of 2001 with copper process capability. By the end of this year, CSP is expected to ramp to its full capacity of ~90,000 200 mm equivalent wafers per quarter, with the majority of its capacity capable of 130 nm manufacturing.

CSP prides itself on its ability to quickly ramp from one process or product to another. "We have the ability to change our technology mix almost instantly," Lam said. For example, 180 nm wafer starts can be increased in lieu of 130 nm wafer starts or vice-versa. "This easy switch is made possible by the use of a common equipment set, same process recipes and operations standardization in all technologies developed at CSP."

In 2000, the first year of CSP's startup, 11 different technology processes/variants ranging from 180 nm aluminum processes to 150 nm copper processes were transferred or developed in CSP. Of these 11, six different technologies under 180 nm aluminum and 180 nm copper technology nodes were fully qualified, enabling the fab to offer a wide variety of processes and flexibility to change the mix immediately after startup. At the same time, a separate dedicated development line was initiated starting with 130 nm copper.

Over the course of the past two years, this mode of operation has continued with new technology nodes having been transferred and developed to allow CSP to offer in production a variety of leading-edge technologies ranging from 180 nm logic and mixed-signal processes, low-power SRAM processes with the world's smallest SRAM cell at both 180 and 150 nm technology nodes, to 130 nm copper dual-damascene logic and mixed-signal node processes.

CSP was the earliest adopter of copper technology in the region, and has successfully tackled the challenges in taking copper damascene into high-volume manufacturing. The fab also has the distinction of being one of the few to integrate the complex dual-damascene scheme into volume manufacturing, skipping the single-damascene option.

Integration options such as via-first or trench-first were evaluated. Unit process enhancements such as feature fill optimization with various copper chemistries, edge and bevel cleaning, copper bath control, and post-ECP anneal were conducted through systematic studies and refinements to processes integration schemes.

"Challenges of implementing copper at the 0.13 µm technology node demanded a great deal of attention to feature size and aspect ratio with specific demands on barrier-seed and copper fill, and superior defect performance," Lam said. "Shrinking dimensions also required improvements in dishing, erosion and post-polish defectivity for copper CMP."

Key features of copper process equipment include the manufacturing capability to span at least three generations, on-site advanced sensors for contamination detection, closed-loop chemical constituent control for copper plating tools, and real-time process controls. In-line ET provides a rapid feedback mechanism, with line excursions being addressed in a real-time fashion. Robust and stringent copper contamination protocols have been formulated and implemented to take into account the multi-technology node operational logistics that support this unique flexibility. In-house development teams working in tandem with the manufacturing groups have enabled accelerated development cycles.

CSP is also an incubation ground for the next-generation 90 nm program, in preparation for the transition to 300 mm manufacturing at Chartered's first 300 mm facility, Fab 7. As part of the initial 90 nm development, CSP took delivery of a 193 nm scanner. In June 2002, the 90 nm unit (baseline) module development was successfully completed, along with 300 mm bridging tool feasibility. The first test chip was first run in CSP in March 2002, demonstrating full functionality six months later.

"The initial 90 nm development learning at CSP proved to be an important foundation when Chartered converged its 90 nm development program with IBM," Lam said. Chartered and IBM entered into a 90 and 65 nm joint-development agreement for 300 mm manufacturing in November 2002. The 90 nm joint-development activity is conducted at IBM's facility in East Fishkill, N.Y., and is in the process of being transferred to Chartered's Fab 7. "We are accelerating our efforts on 90 nm technology development with IBM and ramp up of Fab 7, Chartered's first 300 mm facility, as we prepare for volume production of 90 nm technology in mid-2005."