Demystifying Design-for-Yield

The 0.25 µm through 130 nm nodes taught the industry a few important lessons: 1) Productivity advances in the future would come about not just by feature shrinks, but also by new materials and even new starting substrates; 2) yield ramping and final yields would not reach historical norms; and 3) a key cause of not reaching previously attained yield levels was the gap between design and manufacturing. This article explores design-for-yield approaches and the increasing role they will play in leading-edge device manufacturability.

While it is clear to most people in the industry that design and manufacturing need to be more closely coupled than ever before, many remain unclear on the exact reasons why design-for-yield (DFY) is important today; what the tie is to systematic yield loss; what additional investment is needed, if any, to make DFY a reality; and who stands to benefit from DFY.

First, it is important to define some terms. DFY encompasses design-for-manufacturability (DFM) and design-for-test (DFT). In other words, DFM allows you to precisely replicate on the chip that which is laid out by the design team. However, a manufacturable design is not necessarily a high-yielding design. With DFY, all the test programs and modeling are tuned such that the design, manufacture and test produce high-yielding devices (Fig 1 ).

"Something new and different has to be done to manage the manufacturability of these products at 130 nm and below," said Michael Buehler-Garcia, vice president of marketing at PDF Solutions Inc. (San Jose). Today's DFM solution must go way beyond a design rule check (DRC)-clean design plus some DFT, he said.

1. One of the trickiest aspects of design-for-yield is managing the various forms of data from the different sectors of design, the mask shop, all areas of the fab test, and failure analysis. (Source: Mentor Graphics)

"Given that the process is now a lot more sensitive in the context of shrinking geometries, there is a need for ongoing process monitoring to ensure that the process windows do not shift relative to the models used in design over the lifetime of the technology," explained Sudhakar Sabada, vice president of design technology at LSI Logic (Milpitas, Calif.).

In addition, trends in device physics, such as increased interconnect delay, increasing leakage, and the effects of process variations are each playing a significant role in ultimate chip performance. "The resistance of longer interconnects that are thinner and closer together increases, and you have larger parasitic capacitances. At the same time, sub-threshold leakage current is increasing, which has an exponential dependence on temperature, so it will dominate energy consumption if nothing significant changes in the design process," said Rudy Lauwereins, vice president of the design technology division of IMEC (Leuven, Belgium). "Finally, process variation will force worst-case designs with enormous tolerances that will be unacceptable for large designs. Process variation and leakage issues have already proven extremely challenging for 90 nm embedded memory applications."

In the "good old days," let's say, when critical device features were >0.5 µm, the separation between design and manufacturing was not a problem. In fact, it allowed a level of specialization that was necessary and advantageous. "In the very early days of the industry you had to lay out the transistors with the manufacturing process in mind. And it was only the abstraction of design outside of manufacturing, through the use of design rules, that really enabled the growth of design as its own important contributor to the industry," noted Chris Mack, vice president of lithography technology at KLA-Tencor Corp. (San Jose). "However, today, design rules have become inadequate to describe the manufacturing reality and its impact on the design process."

On the fab side, yield and process engineers managed defects and tool variability, which provided a set of accomplishable designs that were translated through a design rule manual to a DRC deck. The designer followed the DRC to come up with a design layout for a particular device, which, when embodied in a reticle or mask and exposed on silicon, produced yielding chips. During those years, yield problems were primarily caused by random defects, and could therefore be modeled and controlled, given the approximate rule of having to control particles half the dimension of the smallest critical feature.

Somewhere around the 0.25 µm technology node, systematic mechanism-limited yield loss began to show up as a substantial component in yield loss, in addition to random particle-generated yield loss. Today, in early stages of ramping, systematic mechanisms tend to limit yields, including parametric issues and design-to-process mismatch issues. "When you perform physical synthesis as part of the design timing closure flow, you traditionally optimize the metrics of area and timing. These flows have now been enhanced today to optimize for power and yield in addition to the area and timing optimization," Sabada said. "For instance, if there are more robust cells in the library, and if timing permits, you can swap out the less robust cells for the more robust cells."

Systematic defect mechanisms can be introduced from design, process or test; caused by any phenomena with spatial or time-based signatures on the wafer. Systematic yield loss mechanisms include reproducibility problems that can be corrected through tighter process control. But the interaction between the design and process is a key component that DFY targets in sub-100 nm device nodes. These mechanisms, according to sources, are increasing with each device generation and can dominate yield loss.

"Today, people are operating on the leading edge," said Michael Darwin, director of technology development at Rudolph Technologies (Flanders, N.J.). "Random particle excursions are well controlled, and it is the systematic-induced yield loss, often caused by process marginalities, that unfortunately dominate."

"One of the biggest issues we have today are around litho fidelity, particularly throughout the process window," said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division of Mentor Graphics (Wilsonville, Ore.).

The primary drivers for DFM are the complexity of subwavelength lithography, the increasing complexity of design, ever shrinking device geometries, the changes in device structures (dual damascene), and materials that affect the design layout. This article focuses on pattern-induced yield loss rather than material changes such as the changes to copper and low-k dielectrics and their impact on yield, which have been well documented in this magazine.

Some of the most current information collected on yield data is shown in Figures 2 and 3 , from an International SEMATECH-sponsored study of systematic mechanism-limited yield carried out by Professor Rob Leachman and Neil Berglund.¹ The study determined that, while there was considerable variation from company to company, the trends of lower initial yield in manufacturing, slower yield ramps and lower mature yields were consistent throughout the industry with each process generation. This is true even if the latest device generation, in this case 180 nm, is discounted in the interest that it may not have met process yield maturity yet.

2. Data from four logic companies show initial production yield has not observably improved from the 0.5 µm to 180 nm generation, as might be expected from improvements in yield management tools and methodologies. Yield learning rates also have not improved, and mature yields have declined. (Source: Neil Berglund, Northwest Technology Group)

3. Data from 11 logic fabs show the trends summarized in Figure 1 even more clearly. (Source: Neil Berglund, Northwest Technology Group)

"The lack of significant increase in yield improvement suggests that the yield loss mechanisms are increasing in numbers, magnitude and complexity as the industry moves to successive generations fast enough to largely offset the improvements in tools and methodology," Berglund and Leachman observed. Another observation involves the dedication of lot-to-lens — the practice of running all critical layers on a wafer through the same wafer stepper, which has been found to improve yield. This is similar to running several identical mask sets for the same product in the same fab. Although the fab may not know of a specific yield loss signature associated with this practice, it is nonetheless understood that "there are an increasing number of yield loss mechanisms whose root causes reside within the die (or the stepper field), and that they are reflected in fab yield management methodology as increases in inter-die and/or inter-wafer systematic yield loss rather than being correctly identified as arising within the die. Furthermore, these yield loss mechanisms must not be adequately addressed either in the process and mask specifications or in the design rules used by the designers."²

Sabada said, "The conventional wisdom of realizing the smallest die size for improved yields through use of the most aggressive design rules is being challenged now." He gave an example of ways that a design can be improved when the yield failure mechanisms are known: "Design for yield and manufacturability demands attention to detail at every level of the design integration stack. Selective adoption of conservative design rules in IP and chip design without impacting the design objective alleviates yield loss. Use of redundant vias, avoidance of bent gates and incorporating relaxed spacing rules are some examples. In addition, designing IP down to V_dd-30%, as an example, not only improves design robustness, but also enables low-V_dd testing in lieu of I_ddq testing as the devices get leakier."

Resolution enhancement techniques (RETs), most commonly optical proximity correction (OPC) and phase-shift masks (PSMs), are used to reliably create smaller features at a given wavelength or to reduce intra-die and inter-die parameter variations, thereby improving yields. At the 65 nm node, almost every layer will be patterned with 193 nm lithography and some form of reticle enhancement (Fig. 4 ).

4. The increasing rate of adoption of OPC and PSMs. (Source: Synopsys)

"Really, the first tool that tied manufacturing in with design was OPC, where essentially the entire goal is to give you back CD uniformity at nominal dose and focus that disappeared when we started going into subwavelength lithography," Sawicki explained. "What the designer really needs on his desktop is to take a design as they intended — whether a cell or block or chip — and be given a picture of where they have inadvertently created features that will cause the manufacturing people to have a smaller process window and therefore lower yield. Rather than following a set of 'yes' and 'no's, as is the case with strict design rules, we now have 'things you ought to consider doing' and the impact of those changes."

A common example of one such change that is already occurring is double vias — the addition of a via in cases where overlay may be questionable or a via may have a void, and contact between metal layers must be ensured (Fig. 5 ). Another common fix targets CMP dishing in wide features. By inserting metal pillars, erosion is better controlled. However, in both cases, the electrical impact of the changes must be tested to make sure things like chip timing and signal integrity are not adversely affected.

5. Single vias (left) are converted to double vias (right) in the design by preferentially adding onto existing tracks to avoid other possible problems (Source: Mentor Graphics)

"In the case of double vias, people are looking at tools to assess layouts and decide whether they're needed or not and statistically decide how to optimize adding double vias without impacting the die size," said Mike Swayling of Applied Materials (Santa Clara, Calif.). "It may be that only 1% of the locations will make a difference. The trick is to come up with the tools that will predict that and intelligently drop in those extra vias." Another simple change might involve spreading out interconnect lines. Most changes that affect the die size are not acceptable because of the effect on yield.

"Once a change is made, you need to ensure your test tools target that particular fault and the test tool should feed information back to the designer on where failures are occurring so that they can use those tools to model the problems and see if those problems impact the design," Sawicki said.

OPC is being used at about two-thirds of the layers in a 130 nm process, and all the layers of a 90 nm process. The number of rules has risen exponentially and so has the cost and mask complexity. "As a result, we are slowly moving out of a design-rule mode to a model-based mode," Mack said. "The difficulty with this approach is always speed — we need fast, accurate models." Tom Kingsley, product marketing manager for lithography verification at Synopsys (Mountain View, Calif.), summed it up: "The process you need to summarize is too complex to codify in a simple set of rules."

OPC tools typically optimize the wafer image at the best focus and exposure. However, Mack explained that customers began to find OPC defects, or process window qualifier defects, when they printed die at best focus and exposure, changed the focus slightly and printed the die next to the first, then used wafer inspection to compare the two, which gave a defect — a bridge, for example. "You would expect these two images to be virtually identical, and this may only occur in certain geometries, neighborhoods, or a particular style of OPC," Mack said. "We're catching these now on the wafer, but eventually we're going to need the EDA tools to have that capability, accounting for it before the reticle is made."

While attenuated PSMs have become ubiquitous at leading technology nodes, the alternating PSM, which has the ultimate resolution potential, faces severe design problems. It cannot be implemented in manufacturing until "phase conflict" issues can be automatically eliminated from the layout. For instance, a phase shifter on one side of the gate must have an alternating shifter on the opposite side of the gate, which must be automatically corrected in the CAD program. Alternatively, the original design could perhaps be made phase-friendly so that when it is laid out, it would inherently not allow phase conflicts to occur, Mack noted. However, to date, neither approach has been successfully implemented.

6. A new RET closure tool provides better detection of real faults in manufacturing prior to tape-out. (Source: Synopsys)

The trend to model-based data processing is occurring in physical verification and throughout the lithography process. "DRC is a pattern-to-pattern check. We have gone from DRC clean to what we now call DRC closure, where — even after DRC clean — we perform mask synthesis, model-based OPC and simulation, produce the photomask pattern on the computer, fracture it and create the mask," Kingsley explained. "But this mask could have an error that costs thousands of dollars to correct." Through newer, more powerful error check models, scalable distributed process technology, and a user-made library of feature checks, a new RET simulation allows a previously undetected fault to be detected (Fig. 6 ).

Beyond RETs, Chris Progler, CTO of Photronics (Brookfield, Conn.), emphasizes the many other patterning-related yield detractors that are occurring at advanced technology nodes. "We see new interactions between the mask features and the exposure tools because, even if the mask is just as the layout software wants it to be, the way the exposure tool maps the mask pattern to the wafer is more tightly coupled than it was in the past. With the smaller k factor, the mask enhancement factor is one example, and lens aberrations interact more strongly with the mask features, shapes and sizes, than they did previously. In addition, a lot of end users are starting to customize the illuminator for better image fidelity, and this really must be optimized with the mask pattern." All these issues really came to the forefront at the 130 nm node, he said.

One of the advanced studies Photronics is exploring is modeling the relationship between mask dimensions and device parametrics, particularly timing. "We are going after timing because it seems to be the one that is getting the most attention," Progler said.

With regard to metal density variation at the interconnect level, Sabada noted, "The traditional design sign-off at the best- and worst-case process corners based on deterministic modeling is no longer adequate. With the introduction of new materials in semiconductor manufacturing, process control is also impacted by design. As an example, the issue of interconnect variation is a new issue that has to be dealt with because it is now significant. What makes matters worse, is the worst-case interconnect condition does not necessarily occur at the traditional worst-case process corner."

He gave an example of the copper interconnects, where the true worst-case design corner is really dictated by both the device and interconnect characteristics. The interconnect delay is a function of the resistance and the capacitance. When the metal is thinner, the resistance increases, but the coupling capacitance reduces, with the inverse being true when the metal is thicker. The RC time constant determines the interconnect delay. The variation of the metal thickness across the wafer due to CMP and across the die as a result is dependent on the metal density variation that results from IP and chip-level routing.

The magnitude of this interconnect delay uncertainty is now large enough that it impacts the performance of the device in the best case and causes failing silicon in the worst case. "So designers are resorting to multiple corner sign-off at great expense, and affecting time-to-market," Sabada said.

For this reason, LSI Logic has researched and enhanced its timing sign-off delay calculator, incorporating effects of metal pattern density variation based on statistical methods into its best/worst-case design sign-off to minimize impact on designers. "This is a case where manufacturing can have a significant impact on design, and there is a solution on the design side that effectively mitigates the problems on the manufacturing side."

A recent study by engineers at Toshiba³ introduced a new set of multiple-pattern test structures for the 65 nm device generation (100 nm vias), which showed that dummy patterns can be reliably introduced to copper and low-k multilevel metal interconnects to reduce stress-induced voiding failures. The "sea-of-Kelvin" via/interconnect test patterns can be used as a complement to via chain testing, which will not always identify SiV reliability threats.

The matrix of test conditions uses 18 experimental conditions with a sampling of test conditions shown in the Table . Surrounding pattern size, density and location are important to understanding the role of pattern parameters such as via position (borderless or bordered), via misalignment, upper M3 layer interconnect pattern arrangement, etc. The study used two interlevel dielectrics (PAE, k=2.65 and SiOC, k=2.9) and one via stop material (SiCN, k=4.9).

The results showed that the more often the Kelvin via/interconnect structures were located adjacent to open space (Fig. 7a), the more SiV failures occurred. Pattern density of 20% (Fig. 7b ) does not help the failure rate but, at 50% and 80% dummy pattern density, the failure rates drop accordingly. The engineers surmise that perhaps the dummy patterns act as moisture ventilation windows for the low-k dielectrics and protect the PVD copper barrier from oxidizing, which would cause adhesion loss of the barrier to the dielectric and lead to SiV failures.

7. More stress-induced voiding is associated with being surrounded by open space rather than via or interconnect structures (top), and having denser surrounding pattern density (bottom). (Source: Toshiba)

This concept of feedforward and feedback is as much about the tools as it is about the disparate groups involved in subwavelength lithography, including the design groups, EDA suppliers, DFM company, mask suppliers, fab engineers, etc.

DFM is different for each design because it impacts power, area and speed as you tune for yield, Buehler-Garcia explained. "We want the designer to be able to analyze and choose process yield constraints without needing a lot of process engineering knowledge," he said. "If you talk to them about systematic and random defects, their eyes glaze over. They want to talk about what it means in terms of area and performance."

Although the initial benefit of DFY is strongest for fabless companies and foundries, EDA companies, and equipment and mask suppliers also stand to benefit from collaboration. For fabless and foundry companies, it is a question of survival. Swayling of Applied Materials talked about how tool vendors might benefit: "There's what I call a sneaker net in place to communicate design information into fabs to set up inspection or metrology recipes. One of our activities is looking at how to make these more hardwired connections so that design information can help set up recipes, which would be a big timesaving benefit; but then also to communicate areas of the design that may be marginal in terms of design rules or being on a critical path, so that metrology or inspection could focus on those parts of the chip." Such changes would not only benefit the use of metrology and inspection equipment but, ultimately, the use of any pattern-dependent wafer processing tool, including etch, CMP and copper fill.

"We are in the fab collecting the data about how real designs are working in the manufacturing process," KLA-Tencor's Mack added. "We need to feed that back into the design world to understand how well the designs are working in the production line. And, likewise, information about the design can help us understand which parts of the chips are critical and which are less important, so we can change the way we do metrology and inspection, taking into account the meaning of the circuit elements, not just the manifestations of the circuit elements."

Knights Technology, which was recently acquired by FEI Co. (Hillsboro, Ore.), provides software systems that integrate data from all phases of the design and manufacturing process. "Manufacturers have long appreciated the value of collecting and analyzing performance data from each aspect of the manufacturing process," noted David Campbell, Knights' General Manager. "Now shrinking technology is driving the convergence of design/EDA, manufacturing and failure analysis, and this convergence in turn is driving the development of design-to-yield integration strategies. To survive and prosper in the current environment, key design constraints must be fed forward into the manufacturing, and test processes and defectivity issues must be fed back to drive design and yield learning."

To produce chips with high manufacturing yield, the designer not only has to design for good electrical performance, but also has to account for process variations. Berglund suggested three ways the design community could become more involved in the yield improvement process:

• Enhance device simulation capability to include not only inter-die and inter-wafer parameter variations, but also informed values for parametric variations within chips due to intra-die process issues.
• Account for the fact that design rules change over the life of a process. When yield improvement actions are taken, make design rule changes on new designs or redesigns of existing products.
• Work with fabs to include defining new in-process monitors for intra-die parametric variations and relating measurements to yield and IC design. Modify designs for yield testability and yield loss mechanism identification.

IMEC's Lauwereins suggests that increasing leakage current problems and process variations from chip-to-chip and wafer-to-wafer, and their temperature dependence, will drive significant changes in design and design-for-yield. For instance, today, companies make a worst-case design and guarantee at delivery that all chips under all conditions of operation will be able in real time to perform a single implementation of a single application. "However, with variations in transistors, on a die, between die and between wafers, and with temperature variations for a given transistor, you may not know how fast a certain transistor will perform," he said. "Instead, at design time, we can come up with a few possibilities for implementations, each requiring a different number of execution cycles, do a calibration at run-time to determine the actual instantaneous cycle speed of a given chip, and let the operating system select the implementation that currently matches the real-time constant — i.e., whose cycle count multiplied by the current execution time per cycle is less than the minimum required cycle time."

He added, "Process variation definitely starts becoming a nightmare for 65 and 45 nm devices. Using worst-case assumptions is not going to be viable because we will have to run at such low clock frequencies that it will be unacceptable."

IMEC and others are exploring options for addressing process variation, temperature-induced leakage current and ongoing interconnect scaling issues. The translation to and from the design community will be a must for making sub-90 nm design manufacturable and high yielding. "EDA vendors, foundries and IP companies are forming alliances, because it's really a translation between different worlds, and they know that no one member of the four will survive this challenge alone," Lauwereins said.