KGD for Flash Memory: Burn-In is Key

Known good die (KGD) is becoming an imperative for component manufacturers who combine various types of memory in a multichip package (MCP), or who build system-in-package (SiP) devices with processor(s), memory and sometimes even peripheral circuits. KGD assures them that the die in the package have successfully passed extensive testing and been verified as "good," preventing unusable die from cutting into profits by reducing yields. As opposed to die tested only after integration in a package, KGD enables memory manufacturers to guarantee a given quality and reliability level per die before integration and assembly.

As new, high-density manufacturing processes for flash memory are introduced to the market, such as 90 nm technology, the inevitable challenges to bring these processes to maturity present a window of opportunity for assessing and incorporating KGD from the start. Doing so can shorten time-to-market for KGD products.

KGD implementation is time-consuming and costly, even when it is built into the manufacturing process early on. What makes matters more complicated is that KGD is based on non-standard test plans of various levels of rigor. Understanding the benefits and shortcomings of the various test plans and deciding which is best suited to ensure cost-effective KGD is the first important step in its early implementation.

Unfortunately, there is no universally accepted definition for KGD. Generally, it may be defined as a bare (unpacked) die that has been tested and verified as fully functional to meet the full range of device specifications and a certain level of reliability. But different vendors specify different reliability levels for KGD, and sometimes even the reliability feature definitions differ from vendor to vendor. Since the efforts to attain these reliability levels vary greatly, one of the prerequisites in evaluating KGD must be to accurately define the required reliability level.

As many manufacturers have come to realize, KGD is a means to a number of ends, not an end in itself.

One of the most important ends is to enable the high-yield manufacturing of stacked packages, such as MCPs and SiPs. The more die in these packages, the greater the economic loss if a single die is found to be defective only after the package has been assembled. Without KGD, manufacturers may find themselves scrapping multiple good die at final manufacturing stages — when the expenditure in time and raw materials is high — instead of scrapping only a single bad die before assembly. This is especially painful if the defective die is relatively inexpensive, but is part of an SiP containing other costly parts such as processors.

Another end of using KGD is to enable "best of breed" components from a range of manufacturers to be combined in a single unit to achieve a "best of breed" package. If all the die in the package are KGD to meet predefined quality and reliability levels, testing programs for the package can be designed more effectively to focus on combined package functionality rather than on individual die performance. This can save testing time and costs.

Although the benefits of KGD are clear, deciding on the method and level of testing to achieve cost-effective KGD requires understanding current manufacturing practices, standard tests and where they are lacking.

Over the past few years, the number of die that are cut from a typical 200 mm flash memory wafer has increased from 300 to ~ 500, and even more. Although the die are smaller to accommodate smaller end-user products and reduce silicon costs, these die include more circuitry by implementing higher-density flash technology processes, down to 90 nm. Testing for such die consists of several procedures performed at pre-packaging and post-packaging stages.

Electrical testing is performed at the pre-packaging stage as part of the standard testing procedure. Where defects related to bad blocks are identified on the die, a laser repair procedure called fuse blowing is used to try to correct them.

The initial electrical testing is performed at predefined test points to locate gross defects. Electrical testing filters out completely inoperative devices from those that can possibly be fixed. Bad blocks are mapped and replaced, using fuse blowing, with spare blocks that have been expressly set aside for this purpose. Fuse blowing fixes some of these defects; devices that cannot be fixed are scrapped.

Once packaged, the device undergoes burn-in. The package is submitted to several hours of high-voltage stress in an oven heated to temperatures ranging from 125 to 150°C. During this time, designated operational routines are performed on the device. The purpose of burn-in is to eliminate "infant mortality" failures (i.e., traces whose thickness does not meet specifications) by forcing them to occur during burn-in, rather than after the package has left the fabrication facility. Final testing is performed on all packages after burn-in, once again to verify full functionality and compliance with the device specifications.

Because burn-in is such a time-intensive process, it is a central problem for cost-effective KGD. To overcome this problem, burn-in should ideally be performed simultaneously on as many die as possible. Achieving ideal burn-in at the wafer level calls for burning in the entire wafer in one operation. However, each of the 500 die that comprise today's wafer typically has ~ 40 functional pads. Therefore, 20,000 probing points are required to achieve simultaneous activation of all die on the wafer during burn-in.

Placing 20,000 probes on a single 200 mm die is a formidable task, especially taking into account die pad dimensions and pitch, which can be in the sub-100 µm range. Various burn-in approaches are used to try to overcome this difficulty. Each of the approaches has its own technical limitations and cost implications. In the final analysis, the economic effectiveness (measured as the cost per die) of each approach must be examined, taking into account factors such as initial equipment cost, cost of wafer-specific design and manufacturing, amortization and, of course, production volume.

One solution is a full-wafer contact system. In such a system, contact is made with each of the die pads, so that all die on the wafer are activated and burned in simultaneously. A full-wafer contact system can employ one of two methods:

• Probe-per-pad: Each pad can be probed with a separate ultracompact contact "pin" and handled (driven/sensed) independently by testing equipment. This approach is relatively straightforward.
• Sacrificial metal: A thin metallic layer is poured over the entire wafer. This layer serves to connect together corresponding signals of several die to create die groups. Each group is tested for functionality using a reduced number of probes. At the end of the burn-in and test process, the metallic layer is removed by chemical means.

Although a full-wafer contact system allows a large number of die to be processed at once (several wafers may be handled simultaneously in a burn-in oven), such a system has limitations. The probe-per-pad type presents the challenge of designing an extremely dense array of probes; the sacrificial metal type requires additional wafer manufacturing and handling processes to coat the wafer with a metallic layer and remove it. Both types require contactor design per wafer and have significant initial implementation costs.

Another approach is to burn-in and test separate unpacked die instead of the entire wafer. Specially designed sockets can be used to accommodate die after dicing, yet before packaging. The die is inserted into such a socket, which enables burn-in and further electrical testing as if these procedures were being performed on the final package. But, like other methods, such an approach also comes with trade-offs. It requires specific design for each die type, and the socket itself has a limited lifespan, supporting only a limited number of insertions before wearing out.

A solution best suited for higher-density manufacturing processes incorporates a special serial I/O circuit on the die, along with a built-in test (BIT) subsystem. This approach reduces the number of pads that must be probed simultaneously on the wafer by transferring activation and testing signals to the die through a serial link, rather than through a parallel bus. A serial I/O circuit and BIT subsystem require significantly fewer simultaneous probes (a few thousand for a 500-die wafer), compared with probe-per-pad, full-wafer contact systems. Although a serial I/O circuit and BIT subsystem come with the penalty of increased die size and cost caused by additional circuitry and I/O pads, the percentage of additional circuitry becomes lower as die density increases. Since industry trends indicate that die density will continue to increase in the future, this approach will become even more cost-effective. Such a system brings with it yet another benefit: It can be used to perform stress and other tests at one station, whereas a full-wafer contact system requires different stations for different tests. If incorporated early in the design stage for new manufacturing processes, reducing the total number of test stations can further cut costs.

Figures 1 and 2 review the flow of the standard and KGD processes discussed. Because of the numerous approaches, levels of rigor and trade-offs associated with KGD, the decision process for implementing it is a lengthy one. However, once MCPs and SiPs constitute a company's product offerings, KGD will inevitably be required.

1. The standard process for determining KGD.

2. Wafer-level burn-in weeds out bad die before they are packaged, reducing costs.

3. DiskOnChip is a MCP approach that employs known good die.

M-Systems, for example, has been analyzing the possibility of using KGD for some time. It offers KGD a number of its DiskOnChip G2 products, and will offer Mobile DiskOnChip G3 qualified for KGD by the end of 2004. Its family of DiskOnChip-based MCPs, a three-layer drawing of which is shown in Figure 3 , will be available qualified for KGD soon thereafter.