The Wafer-Level Packaging Evolution

The past few decades have seen several basic shifts in electronic packaging that have impacted the whole industry. The introduction of surface-mount technology (SMT) and ball grid array (BGA) packages were important steps for high-throughput assembly of a wide variety of IC types, while at the same time allowing reduction of the pad pitch on the printed circuit board.
 
The ever-demanding trend toward smaller, lighter and thinner consumer products required further package miniaturization. The concept of chip-scale or chip-size packaging (CSP) evolved in the 1990s, and by 1998 four different CSP categories were defined and identified as potentially commercializable: flex interposer, rigid interposer, leadframe-based and wafer-level. In 1998, flex-based CSPs accounted for more than 50% of total CSP shipments worldwide, and no wafer-level CSPs were near production. The literature from that period actually refers to this technology as wafer-level CSP technology.

The obvious benefits of wafer-level packages (WLPs) are that they are fabricated and tested on wafer. It is clear that the cost of the WLP goes down as the wafer size increases and as the die shrinks (same as die fabrication), unlike other packaging techniques that are assembled after singulation of the die from the wafers.

The nascent wafer-level packaging technology of the late 1990s began to reach commercialization in 2000 when our Semiconductor International article declared, "Wafer-Level Packaging Has Arrived ."¹ At this point, there were several competing forms of the technology including:

• Redistribution technology — mainly developed by FCT and Unitive in the United States and Fraunhoffer-IZM in Berlin.
• Encapsulated technology — ShellCSP developed by Shellcase and the microSMT technology developed by Chipscale.
• Flex Tape technologies — such as the wsCSP technology of Amkor and similar technologies from Tessera and others.

This technology has been reviewed in several places.^2-5 As we predicted in 2000, the production capacity that has been put in place in the ensuing four years has been mainly derived from the redistribution technologies. To our knowledge, there are no flex tape technologies in significant commercial production, and while the surviving encapsulated technology, the ShellCSP, has been scaled up by Xintec (Taiwan) and is being used for Sanyo mobile phone imaging chips, it has not found broad general acceptance.

There is still significant confusion in the industry over the nomenclature that surrounds wafer-level packaging. If one examines the simple definition that "...all packaging, interconnection and testing must be fabricated on the wafer prior to dicing," then simple bumped chips could be looked at as WLPs.

Differentiation comes when one adds the further stipulation that the devices are not packaged prior to assembly. Thus, bumped microprocessors and ASICs, which are mounted on chip carriers before final surface mount attachment, are not WLPs. For smaller die and/or die with low I/O, these can be mounted directly on the final substrate, thus these are WLPs. In most cases, the same technology is used for bumped chips and WLPs. Many current foundries offer both "bumping" and "wafer level " or "chip scale" services. Many feel that a true WLP should not need underfiller after assembly, but there are now so many exceptions to this that it should not be used as a criteria. Table 1 shows current wafer-level packaging in production around the world. Table 2 lists institutes working with component manufacturers to develop product-specific WLP technologies.

Devices

Several types of memory are shipped in WLPs, including EEPROM, flash and DRAM. Micron is sampling wafer-level SDRAM for graphics, embedded and wireless applications. Infineon and Samsung are also expected to supply memory in WLPs.

Bourns and Littelfuse have shipped multiple wafer-level diode products used for ESD protection and high-speed signal line protection in hand-held digital products such as digital cameras, mobile phones, MP3 players, PDAs, DSL modems and set-top boxes.

AVX, California Micro Devices, Philips, STMicroelectronics, Telephus and others have been shipping integrated passive devices in WLPs for mobile phones and PDAs.

Fairchild and Maxim are both selling power management devices in WLP form factor such as the Maxim battery management device.

National Semiconductor, an early adopter of wafer-level packaging, has had its own packaging operation in Malacca, Malaysia, which has been operational for several years. Most of their products are available in their microSMD format, such as the supervisory circuit family.

The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) focuses on wafer-level-based back-end processes, such as solder bumping for flip-chip and wafer-level CSPs. Established in July 2000, SECAP is a group of equipment suppliers to the advanced packaging industry. Members include SUSS MicroTec, Semitool, Nexx Systems, Matrix (Axcells), Image Technology, BTU and Ekra. SECAP addresses the development and validation of process equipment for the industry's conversion to wafer-level packaging and 300 mm wafer technology. Within the consortium, the Fraunhofer Institute for Reliability and Microintegration (IZM) in Berlin acts as an independent technology consultant to equipment manufacturers. In addition, Fraunhofer-IZM is an application center for process integration between the different partners' equipment. In July 2003, SECAP finished installation of a complete 300 mm electroplated wafer bumping line at Unitive Semiconductor in Hsinchu, Taiwan. The process flow is shown in Figure 1 .

1. The completely finished installation of a SECAP 300 mm process flow.

The Advanced Packaging & Interconnect Alliance (APiA), a similar association of equipment, process and materials companies, is focused on accelerating the development and implementation of commercially viable packaging solutions that address the manufacturing and performance challenges of leading-edge chipmakers worldwide. Members include Ultratech, Unaxis, Ebara, August Technology and Steag Hamatech, among others.

Compliant technologies for larger chips — The thermo-mechanical board-level reliability of wafer-level packaging based on a pure redistribution is limited by chip size, number of I/Os and distance to neutral point if no underfiller is used. Fraunhofer-IZM, Technical University Berlin and Motorola started a program in 1996 to develop new concepts of high-reliability WLPs. The concept they developed consists of a stacked solder ball array with a stress compensation layer surrounding the lower solder spheres. The observed board-level reliability was 10× vs. single ball analogous structures without underfiller.^5,6 This is shown in cross-section in Figure 2 .

2. A stacked solder ball array with a stress compensation layer surrounding the lower solder spheres.

3. Silicon bumps with redistributed traces were routed from I/O pads onto the top of the silicon bumps. (Source: Infineon)

Another highly promising approach has been announced by Infineon, which has developed a new wafer-level packaging platform to address testing and second-level reliability issues. Since die-level burn-in and test at speed is an expensive step in memory production, the transfer to wafer-level burn-in and test can reduce the overall back-end cost by ~50%. The chipmaker's Elastic Bump on Silicon Technology (ELASTec) is based on resilient interconnect elements on the wafer. These interconnect elements consist of printed silicon bumps with redistribution traces routed from the I/O pads onto the top of the silicon bumps, as shown in Figure 3 .⁷

MEMS Packaging — Wafer-level packaging has been adopted by the MEMS community because packaging of MEMS devices is a major cost issue. Most silicon-machined devices cannot be plastic packaged because molding compound would destroy movable parts or optical sensors. Optical packaging and most MEMS packages share the same basic problem (i.e., the device surface has to interact with the environment without any restrictions caused by the packaging, which at the same time must protect the device from the environment). Wafer-level packaging is possible if the active area of the sensor is on one side of the device and the contacts for the interconnect are placed on the backside of the image sensor chip, for example.

4. The Schott OPTO-WLP process prepares the wafer for ball placement and dicing (Source: Schott).

Schott Electronic Packaging has recently introduced the Schott OPTO-WLP shown in cross-section in Figure 4 . The first step in the Schott OPTO-WLP process is the protection of sensitive active structures by a cover glass. A specialized adhesive wafer bonding process was developed, which enables a selective coverage of the adhesive within the bond layer. In the next step, the bonded silicon-glass sandwich is thinned from the silicon side (backside). The thickness of the silicon is reduced to ~100 µm, enabling low profile, chip-size optical packages for the devices. The actual thickness of the silicon can be adjusted according to the application of the devices; stress-sensitive devices may need a very different residual silicon thickness compared with more robust sensors, where 50 µm residual silicon thickness might be preferred. A plasma etching process is used to structure the silicon. The deposition of dielectric layers over the silicon guarantees the electrical isolation of the following redistribution process, which is based on BCB/Cu or aluminum. After under bump metallization deposition, the wafer is ready for ball placement and dicing.⁸

Post-passivation processing — The potential of integrated passives is obvious if one considers the change in electronics going from single transistors to the concept of IC. Moore's Law was the result of the constant developments in on-wafer technologies. The main difference is that the passives cannot be scaled down to submicrons because of physical limits. In addition, there is a limitation in reducing footprint for integrated passives. The integration of resistors, capacitors and inductors using thin-film techniques on top of the wafers could add further functionality on finished devices wafers. Such technology is in commercial production at Motorola and is being brought to production at STMicroelectronics and many others. Examples are shown in Figure 5 .^9,10

5. A thin-film buildup of integrated passive components (Source: Fraunhofer IZM).