Smart Card Assembly Requires Advanced Pre-Assembly Methods

		At a Glance
	Advanced assembly applications require advanced pre-assembly techniques. For smart cards, thinning wafers and handling thin dice are essential. Packaging the die in the card in a cost-effective manner is also a challenge.

Wafers or dice with thicknesses down to 100 µm are virtually a standard requirement for smart card applications. For a long time now, the most common thickness of about 180 µm has increasingly been replaced by thinner successors. Consequently, there is already a market requirement for "super-thin" dice. In Japan, for example, there are strong efforts to standardize a new generation of contactless smart cards with a final thickness of only 250 µm. It is therefore clear that these cards, with only a third of the current thickness, require extremely thin dice.

Based on these developments it can be seen that the average thickness of a thinned wafer is being halved every two years. So we can expect a thickness of about 50 µm by 2002 at the latest (Fig. 1). This is not far from the ultimate limit. The active layer of a chip takes up only 5-10 µm, depending on the device. For some applications, a certain bulk is needed to assure functionality. So the limit to thinning is in the region of 20 µm, although for some products it may even be possible to reach 10 µm as the final thickness.

Thinning process

The most common process sequence leading to thin wafers is divided into the following steps: taping the wafer's active side, backgrinding the wafer, and etching the backside. Detaping and separation also must be done before assembly.

Taping may be the simplest part of the process block, and it is done to protect the active side. A taping system applies grinding tape to the frontside of the wafer. Here, the wafer still has its original thickness of about 725 µm (for 200 mm wafers), so the risk of breaking the wafer is quite low. It is essential to get firm contact or adhesion between the device side and the tape, especially at the wafer rim. Water and silicon dust penetration between wafer and tape during grinding would crack the wafer, and penetration of acid during spin etching also would damage the chips.

Currently, two main groups of tapes in use are pressure-sensitive tape and UV tape. Pressure-sensitive tape exhibits the same adhesive strength during the thinning process and detaping. The adhesive strength of UV tapes is reduced to about 1-5 % by UV irradiation, which is applied after thinning to make detaping much easier.

Tape often is processed in rolls. In this case it has to be cut on the edge of the wafer, often done with a special heated knife. This method has some problems, such as ragged cutting and scratching of the wafer edge by a misaligned blade. Another idea is to use a precut tape. These tapes already have the shape of the wafer, and you can avoid the above-mentioned problems. It is only pressed on the active side, though, so more care must be taken in positioning wafer and tape to get an optimized result.

3. Etching away grinding damage strengthens the die or wafer.

Grinding typically is done in two steps: coarse grinding and fine grinding. The wafer is ground from the backside using a wheel containing diamonds of well-defined dimensions in a special bonding (ceramics, epoxy or wax). The coarse step removes most of the thickness of the wafer (>90%). This coarse grind causes some crystal damage in the backside silicon. The damage could reach a depth of ~20-30 µm.

The second step takes off only a small amount of silicon (~10%), amounting to only 10-50 µm. The fine grinding step also removes part of the damage that was caused by coarse grinding. However, both grinding steps cause damage to the surface, though the damage from fine grinding is less severe, going only about 15-20 µm deep.

As the wafer gets thinner, it can bow, especially with the influence of all the different layers on the frontside. This effect is amplified by the grinding damage, because the stability of the wafer is reduced. In other words, the grinding process itself leads to a bowing of the wafer.

4. Spin-etching provides more consistent thickness across the wafer than bath-etching.

This bowing is one of the main problems in producing thin wafers. As coarse grinding causes the deeper damage, the maximum bow occurs after this process step. In general it is very difficult to handle bent wafers. This is always a critical job for the equipment handling systems and can result in wafer breakage. Some of the newer equipment types use a modified handling system based on an index table to handle these bent wafers. This table moves the wafer from the coarse grinding station to the fine grinding station without handling the wafer itself. This is a decisive advantage in manufacturing thin wafers.

If wafers are very thin they can even "roll up." As they get thinner, the wafers become more "elastic." It is possible for them to behave like foil or metal sheets. One idea for process support would be to use supporting media, such as plates or other wafers, to hold the process wafer. This is an advantage for handling during the thinning process, but it requires additional processes to apply and remove the support unit. Using a support unit for processing very thin wafers is still in its infancy, and a lot of work remains to be done to make this process usable.

Etching is the next step. As mentioned above, the ground wafers show a strong tendency to bend. In the normal case, the wafers produce a bow that is open at the device side. This stress, which originally is responsible for the bow, easily could be avoided if the grinding damage were removed by etching the damaged silicon on the backside. Figure 2 demonstrates how much bow can be removed by etching. Spin-etching is one way to perform this step. Without additional protection of the device side, it is very easy with a spin-etching system to remove the damaged silicon zone using acidic compounds containing HF and HNO₃.

5. Number of added particles from spin-etching is smaller using Bernoulli handler.

There are other reasons for the etching step in manufacturing thin wafers. One is the enhancement of the die strength. The grinding damage correlates directly with the grinding marks. If these marks are removed you will get much better values in die strength. As shown in Figure 3, the more the damage layer is etched, the greater the improvement in die strength. The best breakage values are achieved by etching to a depth of ~25 µm. In both front and back breakage tests, the 25 µm etched die needs considerably higher forces for breakage than for 3 or 10 µm etched dice. Further investigations show a minimum removal of 10 to 15 µm is required to approach the maximum strength. This also depends on the base material that is used, such as <111> versus other orientations.

Another positive influence etching has on wafer strength is that chipping is "planarized." So those locations where breakage could occur very easily are now quite rare.

A third reason for etching is that it is the only way possible to achieve 20-60 µm thicknesses in a high number of pieces. It is impossible for a high-volume process to grind a 150 mm wafer thinner than 120 µm, and a 200 mm wafer could only reach ~180 µm by grinding. The breakage risk would be very high with grinding. So the last 70-100 µm would have to be removed by a subsequent process for applications needing ultrathin dice.

6. Spin-etching reduces ionic contamination, such as aluminum.

Spin-etching and polishing have been examined for performing this etch step. For an inexpensive, high-volume process, spin-etching technology is competitive and polishing is too slow. Also, spin-etching technology is able to fulfill all requirements in terms of the uniformity and optical quality of the backside of thin wafers. The spin-etching system is very flexible and achieves great advantages in the final thickness uniformity compared with bath etching (Fig. 4). Furthermore, the etched wafers have a near mirror quality, and the grinding marks are reduced to a minimum. Only very rigid, raised marks, called comets, sometimes remain.

Etching of the wafer backside is necessary as a minimum for some products to remove all forms of contamination before the wafers are subjected to subsequent process steps (e.g. power ICs) on the backside. Particles (e.g. grinding dust) or ionic residues often are critical because they are yield-relevant. It is clear that a wet process using chemicals containing HF is ideally suited to solving such problems.

To keep the surface clean after treating with the etchants, it is necessary to avoid any contact with the backside. Here, another feature of the spin-etching tools used by SEZ is based on the Bernoulli principle, with handling forks that guarantee contactless treatment of thin wafers (Fig. 5). The Bernoulli end effector has a nitrogen tube inside robot, centering pins, capacitive sensor for wafer detection, and a light barrier wafer scan. Only at the rim are there several pins that center the wafer in the handling forks to prevent it from sliding off. The qualitative results are shown in Figure 6.

Detaping and dicing

7. Die bond sequences include ejection from tape and placement.

Detaping follows etching, and it is a critical step. Normally, an adhesive tape is applied to the grinding tape and stripped by pulling the tape from the surface mechanically. When UV tape is used, the tape is irradiated for a certain time with a well-defined UV intensity before detaping. Normally, this is done inside the detaping system.

Removing the tape has to be done very carefully. The most important component is an excellent handling system to deal with thin wafers. Fortunately, the etch step has removed the grinding damage and reduces warpage to an acceptable level. When the tape is removed the wafers are extremely fragile, so they must be handled with great care.

The next step is separation of the chips by dicing. Dicing tape is mounted on frames, and the wafers are mounted on this dicing tape, backside down. The wafers now are supported again by tape, and the risk of breakage is low. Cutting is done based on a special set of parameters optimized for thin wafers.

After cutting, the dice are separated on the dicing tape. This is an ideal form for transport. The risk of damaging the chips is now practically zero. The products can be sent to the assembly line, where the first step will be picking up the die from the frame.

Assembly

On the assembly line, the dice are installed in the packages, e.g. smart cards. With the following process sequence, it is possible to support a high-volume process with a yield of several millions of smart card modules per week.

Die bonding is the first step. In this step, each chip is picked up and placed onto the package module, which has been prepared with glue or some other adhesive. From the backside of the wafer, the ejector pin moves upward and releases the die from the glued wafer foil as shown in Figure 7, sequence 1. For this step, it is important that the die's backside, where the die is glued, consistently exhibits very good properties. Now, the bond tool holds the die with a vacuum and places the chip onto the package substrate, which has been prepared with die adhesive. The positioning tolerance is typically <50 µm in the x and y directions. To maintain the electrical performance of the product for NMOS ICs, a dielectric is necessary between backside of chip and metal tape. This could be realized, for example, using a non-conductive adhesive. With chips fabricated in CMOS technology, a conductive adhesive with good processing properties is sufficient to assure the electrical performance of the chip.

The die adhesive is now cured within 60 seconds at a maximum temperature of 150degC. The curing profile has to match with the die adhesive to prevent voids occurring under the chip, which could lead to lower thermal resistance of the product or microcracks during wire bonding.

8. SEM, chip wire-bonded.

Wire bonding is the next step. Here, the die is now interconnected with the ISO contact pads (Fig. 8) of the package. This is effected using a very thin gold wire (~20-25 µm) between 1.5 and 3.5 mm long. The cycle time for complete wirebonding of one die could be faster than 1 second. This naturally depends on the number of wire bonds needed, the wire length and the wire bond technology. The temperature at the substrate has to be over 200degC for this thermosonic bonding process.

Since the maximum thickness for the chipcard module is 600 µm, the loop height (height between chipcard surface and peak of wire) has to be less than 200 µm. Using a special wire bond technology, the loop height can be reduced to about 110 µm.

Encapsulation is done next to protect the die from mechanical and thermal stresses and achieve high reliability for the package. While chemically compatible with the IC surface and substrate (tape), the encapsulant has to be processed without voids within 2-3 seconds in mass production. In smart card packaging, UV-cured encapsulants are being used. Thermally cured adhesives have difficulties with moisture resistance and reliability through temperature cycling. Also, dispensing the correct amount is difficult, leading to unacceptable geometry variations in the final assembly.

A robust encapsulation process has to fulfill the following requirements: good adhesion to substrate, void-free, full coverage of wire and die, low thermal expansion (e.g. silicon-filled), high throughput, single component material and high moisture resistance.

Electrical testing is done on completion of these three steps. After this last quality check, the modules are ready for shipment.

Emerging interconnect technologies

9. Flip-chip technologies include anisotropically conductive foils and various bumping materials.

Flip-chip technology provides the substrate direct electrical access to the die. In comparison mainly with the predominant standard of wire-bonded packages, flip-chip as an interface technology offers a platform for new approaches in packaging. For smart cards, the countless combinations of flip-chip technology can be reduced to the four principles shown in Figure 9.

For connection of the bumped chip into the card, to connect an antenna for example, an anisotropically conductive film (ACF) foil could be used. ACF is an adhesive foil in which small conductive particles are scattered. Each pad of the chip or the package could be connected electrically to the corresponding pad of the antenna by the sandwiched conductive particles. Due to the scattered and well-defined diameter of the particles, short-circuits between the pads do not occur. Today, millions of telephone cards in Japan are produced using ACF interconnect technology.

For contactless chipcards, ACF has been the most promising flip-chip technology because it is much faster than others. Parallel evaluation of wafer-level redistribution is being done. For chipcards with ISO contacts, chip-scale packages are under evaluation. They can significantly reduce cost since they do not require encapsulation or wirebonding. For the system on card application described below, flip-chip technology is the only economical method for making the multipolar connection for the LCD.

Future topics

A new future topic that is attracting a lot of interest from the research and marketing departments of card companies is the "System on Card" (SoC). SoC is essentially a small version of a personal computer implanted on a chipcard. Figure 10 shows a first sample of a System on Card with LCD, biometric sensor and ISO module from Infineon Technologies (Munich, Germany).

10. System on Card provides limited computing along with communications in a card.

These features would offer a lot of advantages and convenience for the customer, so the market volume could rise enormously.² For this application, especially for the packages and their integration into the card, it is necessary that very thin ICs — less than 100 µm thick — are available.

The ultimate requirements for IC thickness are postulated from the future topic "IC in paper".² For this application, which provides an IC thickness down to a minimum of 30 µm (half the thickness of a human hair), the next stage in achieving an even thinner, next-generation IC is opened. A final thickness in the range of 10 µm approaches the physical limits because the active layers of the IC are between a depth of 10 and 30 µm. It follows that the requirement for wafers with a thickness of, for example, 20 µm is obviously the last stage that technology could reach. •

Dr. Jochen Müller received his M.S. in pure & applied chemistry from the University of Regensburg in 1994. In 1996 he received his Ph.D. in inorganic chemistry from the University of Regensburg. Beginning in 1996 he worked for Infineon Technologies as a process engineer in the wet & preassembly departments and in process integration. Since 1999, he has been a senior development engineer for chip modules at Infineon’s chipcard and security IC’s unit.
e-mail: jochen.mueller@infineon.com

Peter Stampka has a master’s degree in mechanical engineering focusing on production technology. From 1994 until 1998, he was responsible for the development of controller modules and chip card modules at Siemens AG (now Infineon Technologies). From October 1997 to October 1998 he worked as senior manager in packaging definition. From October 1998 to December 1999 he was a senior manager with responsibilities in the field of technical marketing. He has been the marketing director of the chipcard packaging center at Infineon Technologies since December 1999.
e-mail: peter.stampka@infineon.com

Werner Kröeninger received his master’s degree in physics with main areas of interest in solid physics, optics and applied physics from the University of Regensburg in 1989. In 1989 he worked as a scientific collaborator at the Frauenhofer Institut (ISC) in Würzburg. From 1990 to 1995 he worked for Rodenstock Precision Optics. After 1995 he worked as process engineer in several fields such as CVD, tungsten and epitaxy for Infineon Technologies. He currently is manager of pre-assembly.
e-mail: Werner.Kroeninger@infineon.com

Ernst Gaulhofer received his master’s degree in electronics & communications in 1983. Before joining SEZ in 1996, he worked for American Microsystems Inc. and Austria Mikrosysteme AG in Austria. Gaulhofer currently is vice president of world-wide process application at SEZ.
e-mail: egaulhofer@sez.at

Heinz Oyrer received his master's degree in mechanical engineering and economics in 1993. He joined SEZ in 1995 to work in technical marketing and was responsible for value-based marketing communication. In 1998 he became marketing manager with responsibilities in the field of product marketing and marketing coordination worldwide. He currently is director of marketing for Europe and Southeast Asia.
e-mail: hoyrer@sez.at

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