The Manufacturing Outlook for High-k/Metal Gates

"When will high-k dielectrics/metal gates be ready for production?" was the question asked at Semiconductor International's latest technology webcast . Answers were provided by Jakub Kedzierski, research staff member at IBM SDRD (Yorktown Heights, N.Y.), Carl Osburn, director of the SRC/ SEMATECH Front-End Process Transition Center, and Jamie Schaeffer, research scientist for Freescale Semiconductor (Austin, Texas).

Schaeffer stated, "Ideally, we'd like to have [high-k/metal gates] ready for high-performance PDSOI applications at the 65 nm node. That is the target." Osburn noted, "Mobility-enhanced strained channels came into play earlier than expected, which has delayed the introduction of high-k, and now the roadmap projects that high-k and metal gates will be introduced at almost the same time."

In some cases, a gate stack can cause changes in device architecture. "High-k may drive the change to FDSOI, because the metal work function requirements for SOI are easier to meet than those on bulk silicon, particularly if band-edge metals are not available," said Kedzierski.

Band-edge metals such as TaN and TaSiN (φ = 3.9-4.3) for n-type and ruthenium (φ = 4.9-5.2) for p-type are required for low device voltage threshold (V_t, low operating power). However, upon annealing, the work function of band-edge metals drift toward the mid-gap. Kedzierski said, "Band-edge metals exist but tend to be too reactive or unstable." High-work-function metals such as iridium (φ = 5.0-5.7) and ruthenium are unreactive, and therefore difficult to etch. Osburn added that they don't adhere well, agglomerate and are permeable to oxygen.

Regarding mid-gap metals, Schaeffer said, "The ramifications of using mid-gap metals for bulk CMOS are exacerbated short channel effects." Kedzierski noted mid-gap metals lead to V_t values that are too high for bulk and PDSOI, making them compatible only with FDSOI or thin-body structures such as finFETs.

Osburn said that charge in the dielectrics complicates extraction of the work function. Tuning, he said, is possible via alloying or ion implantation. A ruthenium blanket deposition, followed by tantalum deposition on the NMOS transistors, can be alloyed. This approach minimizes process steps and avoids the short channel effects with near mid-gap gates.

When asked about the future of silicided gates (FUSI), Kedzierski said, "It is very bright. They offer a bit of work function control, and a fairly easy integration path; they don't use any materials that you wouldn't normally have in the manufacturing flow." The Table summarizes some of the dielectric/electrode combinations.

Schaeffer cited metal gate issues:

• Interface stability during source/drain activation.
• Stable capacitance equivalent thickness (CET) and work function.
• No increase in oxide fixed charge with plasma exposure and no increase in layer thickness with thermal exposure.

For instance, TaSiN has exceptional interface stability with HfO₂. "Unfortunately, ALD HfO₂ crystallizes upon thermal processing. The crystallization process creates HfO₂ grain boundaries that act as pathways for metal diffusion so the metal can react with the substrate," said Schaeffer.

Osburn said that HfSiON is emerging as the leading high-k candidate. HfO₂ has a higher dielectric constant, but the material is highly unstable and has poorer thickness control and the interface stability with metals. He pointed to intense activity to understand charge trapping in dielectrics, its effect on mobility and long-term reliability.