Nanotechnology: Genesis of Semiconductor's Future

Nanotechnology is a science-fiction-come-true infrastructure that bridges myriad disciplines, which offer applications for medicine and road paving alike. For our industry, it hints of a means with which to keep ahead of Moore's Law when our current technology crashes into fundamental walls. Nanotechnology is increasingly dynamic, mutated by biology, surface science, materials and countless other subjects. This convergence is natural because, at the nanoscale, differences between chemistry, materials, physics and engineering fade like echoes — everything works with atoms and molecules.

The semiconductor industry's experience with nanotechnology is not new. Companies like IBM and Intel are in production at the 90 nm node, working toward 63 nm, and eyeing 15 nm — all falling within the common definition of nanotechnology. For this article, rather than focusing upon the industry's standard CMOS scaling experience, we asked some of the leaders of the nanotechnology effort at think tanks and research labs to tell us what they expect things to look like when — and if — CMOS finally joins the vacuum tube in the Pantheon of Great Inventions. What follows are excerpts from those interviews.

Ahmed Busnaina
NSF Center for High-Rate Nanomanufacturing
NSF Center for Microcontamination Control

The approach to making nanodevices split into two camps. Top-down is the brute force approach we use now, where we etch a silicon wafer and deposit various films. These processes are shrinking into nanoscale. The second approach is bottom-up, which uses molecules and nanotubes, and builds up devices to a larger scale. These approaches were considered interchangeable and possibly independent until recently, when everyone realized we must do both. To produce a true nanoscale device you must work bottom-up; however, CMOS may offer scaffolding for bottom-up assembly that will also offer connectivity between micro and macroscale.

The ITRS predicts the industry will use top-down for the next decade. Beyond that, what develops is anyone's bet. By 2015, Intel expects to be working with silicon nanowires and possibly carbon nanotubes. We don't know what building blocks will provide the most robust and commercializable technology.

One company, Nantero (Woburn, Mass.), has brought nanotubes into the fab. Their memory device is similar to Hewlett-Packard's crossbar molecular switches memory device. However, instead of molecular switches, Nantero uses a carbon nanotube switch made by placing a nanotube over a trench and applying an electric charge to engage and disengage it. The nanotube bends to touch the trench bottom and then disengages to go into an OFF state. These nanotubes must be deposited on very specific locations over a large area; however, there's no technology today to do it. A good AFM operator can drag one nanotube and place it in position in under an hour — one nanotube, one switch at a time. Since hundreds of millions of switches may be needed in a device, such method would require millions of hours per device.

Nantero makes switches by creating trenches on a wafer, then coating it with a carbon nanotube film. Using traditional lithography, they pattern and etch the film to create carbon nanotube belts, which may contain hundreds of nanotubes per switch. The belts behave like a single nanotube — they bend, connect and turn off. Once a switch is turned on, van der Waals force ensures it remains there when turned off. It's about 10× faster than flash memory, and unaffected by electromagnetic waves, making it ideal for space and military applications. Nantero is working with LSI Logic — LSI provides the CMOS and Nantero the switches. Within a year or two, they expect to have a nanotubes-based non-volatile memory chip on the market.

Currently there exist three technical barriers to nanoscale manufacturing:

• How to control the assembly of 3-D heterogeneous systems, including alignment, registration and interconnection at 3-D and with multiple functionalities.
• How to handle and process nanoscale structures in a high-rate/high-volume manner without compromising beneficial nanoscale properties.
• How to test nanocomponents' long-term reliability, and detect, remove or prevent defects and contamination.

At CHN, we're working on tools and processes to enable high-rate/high-volume bottom-up, precise, parallel assembly of nanoelements — carbon nanotubes, nanorods, proteins and polymer nanostructures. Current research focuses on surface modification, matching molecules and "sockets" at the level of manipulating a few to several hundred particles or molecules to be assembled into desirable configurations. Commercial scale-up and the promised economic windfall, however, won't be realized unless one can perform high-rate/high-volume assembly of nanoelements economically, using environmentally benign processes.

Our nanotemplates and processes will accelerate the creation of anticipated commercial products, because they're developed with scalability and integration as a requirement. This includes understanding what is essential for a rapid multistep or reel-to-reel process, as well as for accelerated life testing of nanoelements and defect tolerance. This will contribute a fundamental understanding of the interfacial behavior and forces required to assemble, detach and transfer nanoelements required for guided self-assembly at high rates and over large areas.

One project focuses on high-volume room-temperature synthesis of carbon nanotubes with precise dimensions and tunable properties. Another uses bottom-up formation of fullerene nanowires via the supramolecular self-assembly of functionalized fullerenes, to permit nanofeatures with unprecedented resolution (<2 nm separation). In addition, our new methods using nanotemplates for patterning polymer blends at high rates represent an approach especially suitable for commercialization.

One of the center's goals will be the development of template technology to enable the assembly of 100 million or a billion nanotubes in little time. We're working with Nantero to overcome contamination and contact problems, as well as to develop technology to enable them to do single nanotube assemblies instead of hundreds per switch. We're aiming at doing this on a smaller scale by a factor of more than a hundred, and attaining higher densities than is now possible. This is only one architecture that uses switches instead of transistors. There are others, such as molecular gates produced by IBM that use organic molecules as transistors.

Commercial-scale nanotube deposition — and the requisite tool development — is at least five years away. Currently, no one knows how to do nanoscale registration alignment below 10 nm, so we're using chemistry to self-align substrates together. For commercial manufacturing, all the steps are needed — assembly, alignment, registration, functionalization, and reliability tools. Nanotechnology gets considerable government funding because much of it is basic science. Most of what's being done today is scaling of present technology, and the tool companies are not even thinking about bottom-up nanotech tools.

Ilesanmi Adesida
Director of Micro and Nanotech Laboratory
University of Illinois, Urbana-Champaign

People are always surprised when I say we've been doing nanotech for 30 years. In 1976, when I was in grad school, we used e-beam lithography to make 60 nm lines and dots — nanotech isn't new!

What is new is that it's finally getting into devices and spilling over into unconventional arenas. For us, as EEs, nanotech is a natural extension of what we've always done. The mechanical engineer arrived to it by way of MEMS, while the chemical engineer has synthesized molecules since the 19th century. The issue now is how to bring to bear on it the tools and processes developed in electronics over the last 30 years.

Although silicon will be around for possibly another 20 years, there's anxiety over what comes after. Atomic sizes will be attained and we'll be out of dimension. Right now, 90 nm is in line, 65 nm for the next generation, then 45, 30 and 20. Intel has experimented with 20 nm, and gotten some life out of these devices. Of course, it's still far from commercial production.

What comes after silicon? Currently, the carbon nanotube option leads. Besides IBM, schools like Stanford, University of Illinois, MIT, and others in Europe are working on it, achieving interesting results. However, there are still technical questions: How do I grow a nanotube and place it where I want it? As I grow it, how do I ensure it grows into what I want? How do I get nanotubes that behave n or p with silicon's reliability? Nanotubes have issues with surface effects; it took years to solve them for silicon, and this will probably also be true for nanotubes.

Many are tackling self-assembly — the bottom-up approach to nanotechnology — nature's way to pristinely put things together. Bottom-up nanotechnology precisely builds organic and inorganic structures atom-by-atom or molecule-by-molecule. Nature will assemble, but not necessarily how you want it to. There is "directed self-assembly," which imposes a template to get components to self-assemble within it and have the process go in the desired way. So far, we've been able to do electronics using a top-down approach, which is the way we've always made things — from stone axes to spacecraft — by shaping, machining, etching. Using both, researchers pursue an intermediate stage between silicon and nanotube technology. This creates a central area with all directed self-assembled systems, such as nanotubes, to wire them and use silicon in the periphery to communicate with the outside world. This might enable a long-lasting hybrid stage that could give silicon a new lease on life, while we figure out how to get standalone self-assembled nanosystems.

Steve Simon, Director, Theoretical Physics Research
Don Tennant, Nanofabrication Research
Nikolai Zhitenev
Lucent Technologies, Bell Labs
New Jersey Nanotechnology Consortium (NJNC)

Simon: We pursue many fields to understand nanotechnology's basic physics, concentrating on physical effects without considering the devices that might result. It's impossible to predict when our work will shift from science to manufacturing, because we don't know what we'll find — we're on research's ragged edge, questioning things like what is a single molecule's conduction, what kind of quantum and spin devices might be built — not remotely thinking of turning any of this into technology.

Tennant: Some question whether the advanced roadmap's generations can be accomplished. There are roadmaps for 25 nm silicon transistors — that's a half pitch, so it means that there are going to be <25 nm transistors. Scale it and you get heating effects and fabrication issues that exclude necessary precision, uniformity and reliability. I do top-down fabrication on devices and for physics experiments, yet what I'm doing seems more promising than some things in the new device category. Engineers can produce a device as a proof-of-concept in the lab, but one has difficulty imagining the manufacturing techniques that will allow scaling. Excitement is created by the allure of having things self-assemble. It can be done — sort of — with limited geometries, limited number of layers, and limited varieties of complexity.

Simon: It's the difference between making the first transistor and the first IC. At least with the IC there was a vision and a roadmap about how to make it better, faster, smaller. But when you just had a transistor, it wasn't enough.

Zhitenev: Initially, molecular electronics promised much. It originated from chemistry's concept that it's possible to exactly synthesize elements at a scale impossible with traditional top-down approaches. However, once these elements — larger molecules or nanocrystals — are assembled, their interfaces to the macroscopic circuitry are difficult to control. Also, all the semiconductor production common issues such as doping, interface imperfections, etc., are still relevant at nanoscales.

Engineers are back in the lab working on more realistic expectations and device schemes for these molecular devices. Synthetic chemistry techniques will be introduced into the semiconductor manufacturing process, significantly expanding interface design by using chemical bonds on much smaller scales. Although these won't be single-molecule devices, it's reasonable to expect more functions to be fitted into smaller devices.

Tennant: We're working to put together sizable quantum computers. Some of our fabrication facilities here at the Nano Center are exactly what's needed to put together all the little micromirrors, microelectrodes, to move around laser beams and single atoms in a very small space, where they can be manipulated.

All this may be changed by a single development. Remember that the semiconductor roadmap was fairly monolithic for silicon, primarily driven by memory chips. Then Intel came along and, with microprocessors evolving rapidly, CD requirements and microprocessor transistor counts began exceeding those for memory chips. This resulted in two roadmaps: a high-performance logic map, and another for memory.

Simon: Some technologies discussed in conferences are light-years from implementation. People talk about CMOS' end in 15 years, but I wouldn't bet on it. When computers are made for specific purposes, they'll still use mostly CMOS — without fundamentally changing its technology — for a long time, designing chips and power processing for whatever tasks must be made more computationally intensive. This will be far more effective than attempting to develop these proposed technologies, except for some devices for specific purposes.

If you want a single very fast transistor, some of the III-V technologies are already better. Alternative technologies being considered originate from different platforms, different structures, different starting points. Even if they were as good as CMOS (none of them are), you're still short a trillion dollars in investments in getting to CMOS' level. There are changes — not necessarily fundamental — to CMOS, which could have substantial effects upon what can be done at a larger scale. Things like optical interconnects on CMOS chips — there's still a lot of blood left in the CMOS stone.

Tennant: The idea of having all this circuitry and then some highly non-linear system that does some high level of functionality in a very small space, but is difficult to integrate and connect to and so forth, is already seen in the MEMS arena. MEMS are integrated with circuits all the time. Largely, by optimizing both processes and sandwiching them together to make electrical contact. With development funds, we could come up with a process for integrating them in a single stack — taking and incorporating MEMS' functionality (sensors, optics, or any other highly functional thing) and combining it. The idea of foundries that don't just produce CMOS circuits to be taken outside the fab to add a little magic, but instead are equipped for these kinds of integration, isn't farfetched.

And there's experimentation with carbon nanotubes. They've gotten light out of them and made transistors with them. Porous silicon is a possible light-emitting integratable material. All these can result in application-specific, highly functional chips. Hybrid chips — CMOS and nano — will be with us for a long time. Ultimately, that's CMOS' value: the integration and scaling of transistors and high functionality on a small stage.

Alain Kaloyeros, President, Albany NanoTech
Serge Oktyabrsky, Optoelectronics
Robert Geer, Moletronics
Vincent LaBella, Spintronics
College of Nanoscale Science and Engineering, University at Albany

Kaloyeros: Nanotechnology's semiconductor effort took on steam about three years ago when we proposed it under the Focus Center Program. Our mission is to look at scientific innovations that could be used to continue the computer chip's historical evolution during the 15-year timeline. Initially, we educated the semiconductor community regarding the nature of the problems coming down the pipeline with the physics of conductivity and very narrow wires: surface scattering.

Collectively, the Albany team developed a couple of strategies. One was to look at as many innovative ways as possible to determine how far conventional electrical wires and devices can be pushed. The second was to look at the 15-year time horizon and consider potential solutions. One thrust we identified was optoelectronic interconnects, because we think that soon the emphasis will be on off-chip interconnects. This is basically a hybrid structure, where the packaging side is optical and the actual on-chip electrical.

Oktyabrsky: The industry's interest in optical interconnect originated when it was understood that interconnect slows throughput. Compared to the I/Os, a silicon chip's throughput works at a very fast rate — the interconnect slows things down. Optics is very fast, although still bulky and expensive.

The question is how to put III-Vs on the chip and marry both worlds. First off, devices envisioned as transmitters, as well as detectors, are difficult to integrate with silicon. Also, once miniaturized, device parameters are poor. For example, 40 Gb/sec packages for telecom today are based on continuous-wave lasers stabilized at 20 or 30°C, with a lithium niobate electro-optical modulator on an expensive package. Nothing like this can be put on the chip itself, making it necessary to produce small devices and integrate them with the chip.

Of these, vertical-cavity surface-emitting lasers (VCSELs) offer promise, but most optoelectronic devices don't tolerate silicon chips' high temperatures. So a VCSEL that works at high temperatures is needed. However, nowadays, semiconductor lasers are based on quantum wells, with continuous density of states in two dimensions. Thus, when the temperature rises, electrons spread along with this density of states. This decreases modulation bandwidth and degrades gain — the threshold current increases and efficiency decreases. To avoid this, we're trying to substitute quantum wells with quantum dots. Quantum dots are produced using defect-free, few-nanometers-sized crystalline particles. These act as 3-D wells in semiconductors, with localized electrons and holes, and discrete energy levels. This is an advantage, because if you increase temperature, the carriers don't spread, and the gain and most of the other properties are virtually unaffected.

Geer: For the Interconnect Center, the focus is nanowire technology, because when you push electrons into increasingly smaller spaces, you run into fundamental surface scattering problems. This isn't scattering from grain boundaries or interfaces — it's just the fact that, regardless of how well you engineer it, you still have a surface. Depending on how you modify, how you encapsulate a conventional metal such as copper, you can at least move from incoherent to coherent scattering, which isn't as detrimental to the signal. However, eventually you must look at some sort of tailored quantum conduction channel — a single channel to send electrons through, where you keep the transport ballistic or minimize surface scattering. This is the focus of our molecular approaches — designing a material that promotes or creates a 1-D electron channel that you can integrate, compatible with current semiconductor processing.

There's another issue: dimensional variability. As you make things small, say a feature target of 20 nm, the material's in-hand variability makes problematic something as simple as an individual line's roughness, making it perform as an individual interconnect. This has nothing to do with lithography; it's the materials' quantum nature. We've been working on concepts that rely upon directed self-assembly of materials — materials that spontaneously order, or can be directed to spontaneously order on their own, with molecular or atomic precision that can be adapted for electron transport, encapsulation, contact formation, etc.

One attempt uses biomolecular templates. We've been exploiting biotechnology to use the DNA-like natural tendency of biomaterials to spontaneously form. We've been working with polypeptide materials that make beta sheets. These materials form into highly ordered structures we've been modifying to enable electron transport. We've discovered unique self-assembly paradigms that result in 10, 11, 14 nm molecular stable structures across microns.

These are extensions of work done in the bioengineering field, previously ignored in nanoelectronics. Not only can you engineer the materials but also the templates. You can take these bio materials, have them spontaneously form their network, and use them as a guide for conventional metallic materials to get around line roughness issues. We've focused on metal nanoparticles, whether gold, silver or copper, and attached them to a biomolecular construct. This can be done with liquid processing, so we aren't moving into areas too foreign to semiconductor processing.

Kaloyeros: We ensure that the processes we're developing or considering for self-assembly use protocols consistent with emerging or prevailing semiconductor process flows — plating or spin-on — not far-out processes where you pick one carbon nanotube at a time. As with optoelectronics, the semiconductor industry is conservative, and it is doubtful there will be an overnight migration from an all-silicon to an all-carbon-based chip — the transition will be evolutionary. It'll progress from a hybrid where the interconnect might be molecular wire, while the device is still CMOS. Eventually, the move to a complete molectronics chip will take place. We're developing the science with an eye toward current fabrication processes, ensuring that the integration is done in a hybrid fashion.

Geer: Also along this line is the development of metrology and processing technologies. Metrology is a potential showstopper. A major issue is just being able to look at fine features with an electron microscope. You can get depth of field, resolution or low energy, but not all three. Low energy is important with photoresist or any other organic material because you can damage it. People have tried to address this using scanning probe approaches. You fix the problem at one spot, but cannot overcome throughput needs.

We have a multi-pronged approach not just only for inspection metrology, but also nanoscale composition metrology. We talked about looking at nanoscale encapsulation technology and trying to advance and stretch out copper as far as it'll go. An issue with that (which fabs already have) is how to get down a trench to determine whether the monolayer coverage is actually covering. If your line or layer isn't continuous, the plating won't be uniform and the right grain structure won't be there. Currently, these issues are solved through brute force: processing and processing and processing.

A metrology area being considered is environmental SEM approaches — combining gas chemistry with electronic imaging for higher resolution. Another is making optical and electrical probes that give this type of continuity information. It builds upon probe-based CD metrology.

With new material integration, metrology becomes even more critical because we lack the 10 or 20 years of understanding of the material, to where it can be controlled with just blanket control wafers and existing process knowledge. We must come up to speed on it on a three- to five-year timeline, instead of the 30-year timeline we had with aluminum and SiO₂.

Failure analysis is another metrology issue; how to get a real 3-D view of the structure and defects that may develop during processing or use — reliability. We have a program to do that type of 3-D — almost a CAT scan, still in its infancy — just for microscale defects (on the order of 1 µm), but also atomically. In other words, having 3-D atomic information about voids in a metal line, defects in a device, as well as composition — picking out the exact doping profile for a transistor.

LaBella: Using the electron's spin has great potential to produce novel interconnect and device structures for ICs. This idea for "spintronics" sprang from the success of the hard drive industry. When the giant magnetoresistance effect was discovered, a kind of nanoscale device that increases the hard disk drive's read head sensitivity, the storage capacity of hard disk drives exploded. People then envisioned other applications for spintronics. They invented MRAM (magnetic random access memory), a high-speed non-volatile memory architecture, and proposed logic devices like the spin FET, which consumes less power and operates faster than its conventional counterpart. We're also trying to use electron spin for interconnect signal transmission. Spin is present in all electrons, and manipulating spin would use conventional solid-state semiconductor and metal materials — no worries about exotic stuff such as nanotubes or molecules.

It's been shown that spin packets have a long lifetime and high mobility in semiconductors. This makes them attractive for transmitting information in the chip, within the silicon, without using a metal. One of spintronics' biggest problems is temperature. When a magnet heats up, it ceases being ferromagnetic, and ferromagnetism is necessary to couple to the electron spin. Another problem is controlling the ferromagnetism. You can insert a ferromagnet into a device and it'll always be ferromagnetic, with its field oriented in a certain direction. This is hard to change or manipulate.

We've investigated how to make silicon ferromagnetic by implanting it with manganese, making it a diluted magnetic semiconductor (DMS). This has worked for III-V and II-VI materials. Temperature, again, is a problem with a DMS. With GaAs, the highest temperature achieved is ~150 K. Most experiments are done at 10 or 77 K — using liquid helium or nitrogen. We've made silicon ferromagnetic up to 137°C, well above device operating temperatures. DMS materials also have the capability to control their magnetic field strength with an electric field, providing an entirely new circuit element for coupling between devices and interconnects.

Scattering is another challenge facing spin use. You can generate a spin-polarized current in a diluted magnetic semiconductor region, and transfer it into a non-magnetic region to manipulate it. However, considerable scattering (spin flip scattering) occurs at those interfaces. We're just beginning to understand the physics behind these scattering mechanisms, and need nanoscale probes to isolate these defects and measure the spin scattering rate. Measuring the spin polarization state is challenging.

While it's simple to measure current using any off-the-shelf current meter, you cannot measure current's polarization with any off-the-shelf device. This poses difficulties when you want to measure scattering mechanisms for spin. To overcome these difficulties, we've developed several nanoscale spin transport probes. These probes are based on a combined ultrahigh-vacuum scanning tunneling microscope (STM) and molecular beam epitaxy chamber. We can fabricate both silicon and GaAs layers, dope them, make them ferromagnetic, deposit ferromagnetic metal on them, and perform all the spin measurements in situ, without breaking vacuum.

We've modified the STM, which can be cooled to 4 K, to do experimental techniques that probe spin transport. These techniques leverage the STM's atomic-scale precision to get the requisite nanoscale knowledge base that is needed. The big push for the future of spintronics is to develop spin-based devices that can be integrated with conventional electronic devices, materials and manufacturing processes. Spintronics has considerable potential, and I think we're only at the beginning of some very exciting times.

Mihail Roco
Chair of National Science and Technology Subcommittee on Nanoscale Science, Engineering and Technology
Senior Advisor for Nanotechnology, National Science Foundation

In 2000, I estimated that by 2010, worldwide, about $300B worth of semiconductor production would be nanotechnology-based (including nanocomponents such as nanolayers, nanoscale treated materials, or other nanostructures). So far, this estimate is holding. By 2015, we estimate it at about $500B. This means major applications of nanotechnology. By then, we'll also move beyond traditional CMOS. We're already building devices and components that work with CMOS. There will be a transition period from CMOS into another kind of device that, right now, we cannot even begin to describe.

Because nanotechnology can reduce its basic features, CMOS will continue being used for a decade or more. Although the current production range is at 90 nm, 5 nm gates have been proven in labs — of course, we don't yet know how to manufacture them. The intermediate future will have CMOS married to a generation of nanodevices as yet undefined, because there are many alternatives, and it's still too early to tell which will prevail.

As we approach 2015, semiconductor development priorities will change. In 10 years, the focus will shift from scaling and speed to system architecture and integration, with user-specific applications for bio-nanodevices, the food industry and construction applications. Another trend is the convergence between IT, nanotechnology, biotechnology and cognitive sciences. The higher speeds at which information will be disseminated will change how we work with computers, and also perhaps how we deal with things like damaged nerves, possibly by developing direct interfaces with the nervous system and electronic circuits. This is neuromorphic engineering, where signals are directly transmitted from a human organism to a machine.

Now, it's a question of which of the many new ideas are feasible — economic to manufacture. We still have a long way to go before we sufficiently understand the physics involved, to be able to measure the nanoscale, to manufacture. The major problem is which approach to choose: spin electronics, molecular electronics, biocomponents, quantum computing, DNA computing, etc. Any scientific discovery could overturn everything. When IBM introduced giant magnetoresistance in 1998, limited use was predicted for it. However, it was so superior that in two years it replaced all equivalent hard disk reading technologies and their extensive production facilities.

Before 2002, nanotechnology was somewhat of a pipe dream. Since then, nanotechnology investments have greatly increased.

The field of nanotechnology applications is now dominated by large companies that lead the market and make and sell their products economically. Like in bio-related fields, small companies are tempted to target emerging technologies that don't yet have the infrastructure, but they have a harder time because they lack long-term investment capital. These companies look for the new generation of products, of which there are four.

The first generation was passive nanostructures. It saw the creation of commercial prototypes and the acquisition of systematic control at the nanoscale for these products. These first products had a "passive" nanostructure (nanostructure polymers, wires, coatings, etc.), and made their appearance around 2001. They're now in commercial production.

The second generation will be "active" nanostructures — devices such as actuators that behave like muscles; transistors with active parts created by design; drug delivery within the human body at specific locations and times. All of this is already in advanced R&D, and we'll see some of it (at least commercial prototypes) next year or soon after. Active nanostructure devices will lead to a significant market expansion.

The third generation will arrive around 2010 when nanodevices and nanomaterials are integrated into larger nanosystems, and systems of nanosystems with emerging behavior will be created as commercial prototypes.

From 2005 to 2020, we'll begin seeing fourth-generation large nanosystems whose different components will be molecules or macromolecules. This approximates how living systems work, except that living systems are more complex, being integrated on lengthier scales, generally use water, and grow slowly.

We're currently researching all four. The integration level will be incredible, and there will be more systems of nanosystems than few separate devices for electronic circuits and transistors. We may have various pathways to larger systems such as nanorobotics with emerging behavior, biomimetics, guided self-assembly, and evolutionary approaches.

We're beginning to build different types and new assemblies of molecules.I can see a transistor being like amacromolecule, doing all the functions, or as a macrocrystal. The key change will be the integration of these components. Today we speak of a single transistor integrated with a microwire. Even on the nanoscale, you need a typical means of integration. I see a system where you begin with nanotransistors and other nanosystems, building the final product in situ, without later assembly.

Self-assembly will be the core of most processes to build nanostructures. It allows you to create molecules that create macromolecules that, in turn, allow the bottom-up creation of devices with the desired properties and functions, in precise and economical ways.

There will be tools — nanosystems — capable of producing things. However, manufacturing at a nanoscale cannot be done by other nanodevices because, being so small, they cannot transmit energy or materials. Nanoscale/macroscale integration will continue to be essential. Mechanical assembling of nanosystems by other devices seems unlikely in manufacturing processes. There will be methods such as directed self-assembly, guided by magnetic, electric, chemical and thermal methods.