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Wafer-Level Packages to Include Solder Ball Support

John Baliga, Associate Editor -- Semiconductor International, 11/1/2000

At the advanced technology workshop on chip-scale packaging held by IMAPS in September, a session on wafer-level packaging revealed an interesting trend: Many wafer-level packages use solder ball area arrays for I/Os, and now some of them are providing mechanical support for the solder balls to improve reliability.

Wafer-level packages based on solder ball area arrays have been thought of as glorified flip-chips, with a polymer or other material providing mostly moisture resistance. They have typically used a large solder ball to take up stresses from CTE (coefficent of thermal expansion) mismatch. Though good moisture resistance has been demonstrated for these devices, thermal cycling tests have not always been adequate. Now the packaging done at the wafer level is helping the solder ball take up some of the CTE mismatch stress. Though the added material does not necessarily take up the stress, the solder ball is supported to help prevent solder joint failure on the die.

Flip Chip Technologies (FCT, Phoenix) has developed what it calls polymer collar technology as an addition to its Ultra CSP package (Fig. 1). A polymer material is added that wets up to the solder balls, forming a supporting collar.

At the workshop, the company reported temperature cycling (-40/125°C, 1 hr/cycle) results for RDRAM test chips with 0.8 and 1.0 mm pitches and a 5.95 mm maximum distance to neutral point (DNP). The Weibull life was 744 cycles without the collar, 1120 cycles with the collar.

1. Polymer collars help to extend temperature cycle reliability for FCT's Ultra CSP. (Source: Flip Chip Technologies)
The Fraunhofer Institute for Reliability and Microintegration (IZM, Berlin) presented results of a packaging technique they developed for Motorola, and reported originally at this year's ECTC. Called fab-integrated packaging (FIP-SCP), the process starts with a typical redistribution using high-lead solder, which is screen-printed and reflowed. A filled epoxy material is applied to the bumped wafer, covering the solder balls. The material is applied over each die individually, leaving the street areas open, which helps to keep stress from building up on the wafer.

A CMP planarization is then done, exposing the underlying solder balls (see "Wafer-Level Packaging Has Arrived," Semiconductor International, October 2000). Eutectic solder balls are placed on the exposed high-lead balls and reflowed. This double-ball approach produces a package similar to a typical flip-chip or wafer-level package, and the high-lead balls act as compliant leads rather than compliant I/O contacts.

Motorola also presented its adaptation of the technology (Fig. 2). The first solder ball is eutectic solder, and a customized stress compensation layer (SCL) material is applied by squeegee printing. Instead of planarization, a hole is developed out of the layer to expose each solder ball. The street areas are also opened up to prevent stress build up. Preformed balls are then placed and reflowed. The hole formation process is engineered to ensure that the remaining SCL material maintains tight contact with the solder ball.

2. Motorola's wafer-level technology. (Source: Motorola)

Various ball sizes were studied, and the best results came when both solder balls were the same size. When one ball is larger than the other, the larger one tends to "steal" from the smaller. Motorola also has been working with FAS Technologies (Dallas) to use an extrusion process for dispensing the SCL, with cost savings through reduced waste as the motivation. .


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