Applying Equivalent Scaling to USJ Implantation

As the semiconductor industry scales devices beyond 90 nm to the 65 nm node, traditional ultrashallow junction (USJ) scaling will drive implantation energies to ultralow energies of 200-500 eV. Such a change requires fundamental redesign of existing high-current beam line implanters to reduce energy contamination and improve productivity. This can be avoided by using implant-equivalent scaling similar to gate dielectric equivalent oxide thickness scaling. In p-type doping, for instance, a change to a higher-mass dopant species from boron to B₁₀H₁₄ or B₁₈H₂₂ increases the effective energy and beam current by 10-20×. This change is analogous to the replacement of SiO₂ gate dielectric with high-k dielectric to improve gate leakage by orders of magnitude while increasing physical gate thickness by ~3×.
 
From an implanter equipment standpoint, batch end-station designs for high-current, low-energy ion implantation are becoming problematic because of the cone-angle shadowing effects that limit gate length (L_g) scaling caused by asymmetrical transistor formation, and the high-rotational-speed spinning disk, which causes particle-induced poly structure failure. The use of molecular dopant species (B₁₀H₁₄ or B₁₈H₂₂) enables low-energy, high-dose single-wafer implantation using scanned beam with 1-D mechanical scanning. This approach can eliminate shadowing and energy contamination, is self-amorphizing and reduces channeling without end-of-range (EOR) damage, thereby eliminating the need for a separate pre-amorphizing implant (PAI) step.

A total implantation angle variation of <0.1° across a 300 mm wafer is required for continued L_g scaling, including effects from both beam divergence (also known as blow-up) and tilt angle. Kawasaki et al. and Wan et al. have reported on these beam angle variations caused by cone-angle effects on batch end-station designs and how to reduce these effects.^1,2 One solution is to switch to a single-wafer end-station design. Three different single-wafer designs were reported at the 2004 International Conference on Ion Implantation Technology: 1) broad/ribbon beam with 1-D mechanical scanning (VSEA VIISta-80)³; 2) spot beam with 2-D mechanical scanning (AMAT Quantum-X)⁴; and 3) scanned spot beam with 1-D mechanical scanning (Nissin Exceed).⁵ The third method is achieved on the Exceed medium-current implanter by applying equivalent scaling philosophy and using molecular dopant species, which represents a new classification of implanter called multi-purpose implanter (MPI). By using molecular dopant species, all CMOS device implantations (Fig. 1 ) between 100 eV and 750 keV can be performed on this scanned spot beam single-wafer implanter. Angle variation across a 300 mm wafer is reduced to <0.1° for tilt angles from 0° to ±60° with a mechanical throughput limit of >375 wph.⁶

1. A multi-purpose implanter uses a scanned spot beam and a single wafer to achieve the above implants at energies ranging from 100 eV to 750 keV.

HALO scaling — To improve short channel effects and minimize HALO overlap under the channel (thus preventing mobility degradation), HALO implantation energy is decreasing to the 1 keV energy range, while the dose is increasing to the mid/upper 10¹³/cm² range. Lower implantation energies lead to increased beam divergence and reduction in beam current (implanter productivity). Therefore, one solution is to go to higher-mass dopant species, allowing for higher implantation energies using In, B₁₀H₁₄ or B₁₈H₂₂ for p-type species, and Sb, As₂, P₂ or As₄ for n-type species. Umisedo et al. reported that, at the same equivalent low energy of boron, B₁₀H₁₄ reduced beam divergence angle 12× from 1.2° to 0.10° and beam size 11.4× from 139 mm to 12 mm.⁷ These higher-mass HALO implants can also induce amorphization if the dose is high enough. In addition, high-tilt channeling angles need to be avoided because of channeling along the lattice planes; (210) channeling at 26.6°, (320) channeling at 33.7°, (211) channeling at 35.5° and (321) channeling at 36.7°.

Source drain extension (SDE) scaling — Another aspect of L_g scaling is USJ SDE formation. Issues with USJ formation include energy contamination, channeling, EOR damage (which degrades junction leakage), and annealing to reduce dopant diffusion and increase electrical activation above the dopant solid solubility limit.

The Table  shows the implantation energy for various boron dopant species to achieve the as-implanted junction depth (x_j) of 15 nm for the 65 nm node and 9.5 nm for the 45 nm node — assuming a 10¹⁵/cm³ dose and 10¹⁸/cm³x_j definition. A 500 eV boron implant into a PAI structure is required to achieve the 15 nm junction depth target at the 65 nm node without channeling using diffusion-less activation annealing.⁸ With a 1050°C spike anneal, ~15 nm of diffusion will occur, so <100 eV implant would be needed and the anneal temperature should be reduced to 900°C.⁹ At such a low energy, deceleration mode implantation would be preferable to get higher beam currents and improved productivity, but because energy contamination (EC) gets worse at lower energies and devices become more sensitive to EC with L_g scaling, the drift mode is preferred.

Typically, <0.05% EC is required, depending on specific product type, as reported by Kase.¹⁰ Because the channel-doping level range for 65 nm node high-performance (HP) logic is 2.5-5.0 × 10¹⁸/cm³, and for low operating power (LOP) and low standby power (LSTP) logic is in the 0.8-2.0 × 10¹⁸/cm³ range, very low levels of EC are required.¹¹

Wafer end-station scaling — Two detrimental effects on L_g scaling have been reportedly caused by batch high-current end-station designs. In the first example, variation in incident beam angle across the wafer results in asymmetrical SDE implantation caused by implant shadowing from the gate-stack structure — especially for close gate-to-gate spacing as reported by Yoneda and Niwayama and shown in Figure 2 .¹² The second effect is unique to wafers subjected to high-speed spinning disk, which can cause catastrophic poly structure failure for L_g <100 nm due to interaction with beam borne particles, as reported by Kawasaki et al.¹³ Reducing the disk spin speed from 1200 rpm to 220 rpm decreases this problem, as reported by Pipes et al.¹⁴ Once the poly-side wall spacer is formed, this failure mode is eliminated, so it is an issue only for the HALO and SDE implantation steps requiring single-wafer implantation.

2. Gate shadowing, which leads to asymmetrical transistor formation, has reportedly been caused by batch high- current end-station designs.12

Gate overlap — A final issue with L_g scaling is SDE gate overlap control. As lateral diffusion is reduced, implant dopant lateral straggle is no longer sufficient to achieve the desired lateral gate overlap. Therefore, both tilted SDE and PAI implantation up to 30° will be necessary to achieve a 0.5× lateral overlap, as reported by Borland et al., Lindsey et al. and Thirupapaliyer et al.^15-17 Device simulation results on NMOS device drive current improvements for increasing SDE tilt angle and gate overlap is shown in Figure 3 .¹⁵

3. Device simulation results on NMOS device drive current improvements for increasing SDE tilt angle and gate overlap.15

In the past couple of years, molecular dopant species with high beam current (14 mA) and >100 hr source life have been reported by Jacobson et al.¹⁸ They reported 500 eV equivalent beam current of 5 mA using B₁₀ H₁₄ and 10 mA using B₁₈ H₂₂. For a 10¹⁵/cm² dose on 300 mm wafers, this would result in a throughput of 95 wph with B₁₀ H₁₄ and 172 wph with B₁₈H₂₂, compared with drift mode boron of 15 wph. SIMS results for 500 eV/10¹⁵/cm² boron profiles are shown in Figure 4 for crystalline and PAI wafers. A reduced channeling B₁₀H₁₄ profile can clearly be seen in the 17 nm junction, and self-amorphization was verified by cross-sectional TEM (Fig. 5 ).⁵ Molecular dopant species eliminates the need for a PAI implant step, and no EOR damage could be seen after annealing.⁵

4. SIMS showing non-channeling, self-amorphization with B10H14.5

5. Boron vs. B10H14 cross-sectional TEM shows self-amorphization of 3 nm for 500 eV/1015/cm2 equivalent boron.

Figure 6 shows improved dopant activation results for sheet resistance vs. junction depth for B₁₀ H₁₄ using 500 eV equivalent implants. Therefore, as shown in the Table, the 65 nm node x_j target of 15 nm will require a 200 eV boron implant into crystalline silicon or a 4 keV B₁₀H₁₄ or 8 keV B₁₈ H₂₂ implant. A 4 keV B₁₈ H₂₂ implant is shown in Figure 7 with an x_j=11 nm.

6. B10H14 can achieve lower junction depth following 900-1050°C anneal than the energy equivalent B implant.5

7. To meet the needs of the 65 nm node, a 4 keV B18H22 implant can attain an 11 nm junction depth with reduced channeling.

Applying equivalent scaling by using molecular dopant species on the Nissin Exceed medium-current implanter has realized low-energy, high-dose implantation critical for continued L_g scaling to 65 and 45 nm nodes. Molecular dopant species implantation extends the medium-current implantation application space into the low-energy, high-current space and enables high-tilt SDE without PAI for gate overlap control caused by its self-amorphization and reduced channeling effects. This new MPI using scanned spot beam with 1-D mechanical scanning is capable of performing all the implants for advanced logic devices using epi or SOI CMOS technology for equivalent energies between 100 eV and 750 keV at 0-60° tilt angles.