3-D Packaging Enables New Stackable CSP Designs

Cell phones and other applications have created the need for more innovative chip-scale packaging (CSP) solutions. At first, CSP or fine-pitch ball grid arrays (FBGAs) with <0.80 mm pitch was adequate. However, wiring restrictions on PCBs and package interposers dictate that 0.50 or 0.40 mm is the minimum practical pitch for CSP, making it increasingly difficult to achieve higher package density in X and Y. System designers are now forced to pursue 3-D package alternatives, exploiting the Z dimension, for cell phones and most other compact consumer products.¹

Evolution from cell phones with only a base-band processor and limited memory to today's high-end phones with an additional applications processor and memory has driven the industry to 3-D packaging solutions.

3-D packaging can be achieved via die stacking in one package, package-in-a-package stacking or package stacking (Fig. 1). Each method has its pros and cons (Table 1 ). Overall:

• Stacked-die CSP (S-CSP) has been widely accepted for many cell phone applications, because this solution exploits the Z-space (i.e., height) while maintaining its X and Y footprint with little, if any, increase in package thickness. The major drawback to S-CSP is that, if one of the stacked ICs fails, all the assembled dies are lost.
• Package stacking, which has been researched in a variety of formats^2,3 (Fig. 2 ), enables stacking of die from different suppliers and mixed IC technologies. It also allows for burn-in and testing prior to stacking.
• Package-in-package stacking involves flipping and stacking a tested package onto a base package, with subsequent interconnection via wire bonding.⁴ The assembly processes for package-in-package stacking is similar to S-CSP. A package-in-package requires an additional surface-mount stacking process at board assembly.

1. 3-D packaging can be achieved via die stacking in one package, package-in-a-package stacking or package stacking.

2. The package stacking options for chip-scale packages (CSPs) have been researched in a variety of formats.

"Ownership" can be an issue surrounding these methods. Because IDMs build package-in-package and S-CSP products, OEMs cannot necessarily select memory and logic ICs separately, unless it is done via special development. On the other hand, an OEM can stack any memory IC package on a separate logic package, even one offered by a different IDM, as long as the footprint matches. Although OEMs need to stack packages using dedicated pick-and-place equipment during board assembly, flexibility in system configuration, down to the individual component, is gained. For instance, the OEM can fix memory density just before launching a final product.

Key assembly technology

Successful 3-D packaging has resulted from both evolutionary and revolutionary advances in core wafer-level and package-assembly-level technologies. Chip thickness control, for example, is critical to realizing a very thin mold cap for package-on-package solutions. For wafer thinning, backgrinding to <100 µm is not difficult by itself. However, the thinning process must be optimized to ensure functional die quality and reliability. During mechanical wafer backgrinding, stress can be easily induced through silicon grain deformation, leading to reliability (e.g., die cracking) and processing problems (e.g., handling warped wafers). Fine polishing is required to eliminate silicon-grain formation; several technologies have been proposed, such as CMP, wet etching and plasma etching. Table 2 shows die warpage control and surface roughness levels that are possible with advanced wafer thinning processes.

Wire-bonding technology is a key factor that determines the minimum mold-cap thickness for package-on-package and die stack-up height for S-CSP. Low wire loop and long wire bond clearances, between the die surface and the mold cap, can appear to be very narrow for wires coming out of die bond pads. Whenever the clearance is >0.3 mm, the gap is sufficient and conventional ball bonding technology can be used; it enables high productivity and good bonding quality. However, low-profile requirements, with multiple die or packages in 3-D packages, often require clearances <0.3 mm, so different wire-bonding technologies must be applied:

• Ball bonding technology has continuously been improved to reduce wire loop profile.
• Standoff stitch bonding (SSB) first uses a ball bond to the bond finger and, second, a stitch bond to the die pad where a gold stud bump has previously been formed. This technology allows for wire loops <100 µm without damaging bond wires. Compared with conventional ball bonding, productivity is lower because of the longer bonding sequence.
• Gold-wedge bonding can produce loop heights <75 µm, but the bond pad pitch must be larger than for typical ball bonding.

Overall, the substrate bond finger design and the selection of the wire bonding method require careful study before finalizing the design.

Because there are many parameters to be considered, assembling multiple die inside a single package requires more advanced technologies than those used for single-die assembly. Package cost and performance, including manufacturing yield, mechanical strength, reliability, thermal and electrical properties, are directly affected by the overall package design; special focus is required in early development stages.

One issue, for example, may be top-die rotation and its effect on the package design (Fig. 3 ). Although a larger package is required in the one case, lower-cost design rules may be used because of the extra routing area. Wire bonding and molding are challenging technologies when there is die overhang; however, there may be no need for a spacer between the two die since the bonding pads of the lower die are far enough away from the edge to allow the upper die to be bonded. These types of decisions are required prior to substrate design.

3. Top die rotation and its effect on the package design.

As the complexity of die stack increases, choosing the appropriate die stack up and subsequent substrate requirements dramatically increases in complexity for each new package design.

To enable package stacking, the mold-cap thickness of the bottom package must be less than the solder ball standoff height of the stacked top package. For CSPs with 0.5-0.8 mm ball pitch, 0.2-0.4 mm ball standoff height has been widely adopted in compact applications, necessitating thin molding technologies.

Figure 4 shows calculations for the solder ball standoff heights, before and after reflow, to attach the stacked packages, as it is predicted from the volume of solder. It is assumed that no solder paste was used, and only flux was applied on the pad for the package-to-package reflow attach process. This assumption was made because any screen paste printing would be difficult. To get as large a standoff height as possible, 65% of CSP ball pitch was selected as the practical ball diameter. Large solder balls can cause bridging during the assembly or board mounting process. For 0.65 and 0.5 mm pitch CSPs, the diameter of original solder ball is 0.42 and 0.33 mm. Under the condition that the solder mask opening size is half of CSP ball pitch, the standoff height after package stacking is 0.28 mm for 0.65 mm pitch and 0.22 mm for 0.5 mm pitch CSP. The mold-cavity thickness must then be determined by the required standoff height. The standoff height is ultimately a function of the size of solder mask opening and ball diameter.

4. Calculations for the solder ball standoff heights, before and after reflow, to attach the stacked packages, as it is predicted from the volume of solder.

Conventional molding, where the resin is injected from the side of the package, sacrifices the ball count of the stacked top package because it is not possible to design pads for solder joints in the molding-gate area. To enable a thin-mold cap and maximize pad count, top mold-gate technology has been developed for the bottom package in package-on-package format. Because the position of the mold gate is located at the center of the package, resin flow does not cause wire deformation, such as wire sweeping.

Using these newer concepts in assembly technology, we have developed two new types of package-stackable CSPs (Fig. 5 ): One is similar to conventional plastic BGAs and the other has a cavity at the center of the substrate.⁵ Both packages have copper pads on their top surfaces along the molded area so that another package can be stacked on top.

5. Two new types of package-stackable CSPs: One is similar to conventional plastic BGAs, the other has a cavity at the center of the substrate.

The first uses 100 µm thick die and ultralow loop wire bonding. Top-gate molding was used to maximize the number of solder lands for interconnecting a top package around the finished mold-cap area. Using a standard solder ball size of 0.30 mm for this 0.50 mm pitch CSP, the maximum overall package profile height, after board mounting, is 0.8 mm, assuming a 0.27 mm thick mold cap and a four-layer thin-core substrate. Therefore, a 0.65 mm pitch CSP having 0.42 mm diameter solder balls can be stacked on top of it.

The second, because the die is placed in a cavity, uses a 0.20 mm thick mold cap, resulting in a total height of 0.65 mm, assuming a 0.20 mm thick, two-layer substrate. For this package, a 0.5 mm pitch CSP with 0.33 mm diameter solder balls can be stacked.

Compared with a cavity-style package, obviously, the no-cavity package is thicker, a disadvantage for compact applications. However, routing of the substrate is very flexible using four-layer advanced design rules. Because the bonding pads are typically not well aligned between memory and logic ICs manufactured by different IDMs, this routing advantage can be a major factor in package design.

During our development work, we looked at a variety of molding compounds to minimize package warpage. Because of individual unit mold format and the flexible thin-core substrate, warpage can be severe in cases where the coefficient of thermal expansion (CTE) of the mold compound is not well balanced with other packaging materials. Figure 6 shows the relationship between the molding resin CTE and package warpage, normalized to package body size. This data shows that warpage is strongly dependent on the CTE of the resin.

6. The relationship between the molding resin CTE and package warpage, normalized to package body size, is shown. This data indicates that warpage is strongly dependent on the CTE of the resin.

Because of package structure, the warpage of the cavity package was always concave, while that of no-cavity package was convex.

In the cavity-style package, the die is located in the lower portion of the structure, resulting in very low effective CTE compared with the mold compound. Therefore, the cavity package always shows concave warpage after cooling from the stress-free point (~175°C at mold cure) to room temperature. Also, using a mold compound with a lower CTE is an effective solution for improving warpage, as the CTE mismatch can be reduced.

The no-cavity-style package has only the substrate material in the lower portion of the structure, while the upper portion contains the die and mold resin. Since the CTE of the die is lowest, the upper portion has a low CTE, while the lower portion acts with the properties of the substrate only. For this package, a higher CTE molding compound will work to reduce the overall warpage.

Consequently, different mold compounds should be chosen for each package. Since both package styles tend to flatten at high temperature, such as during reflow, package stacking is successful using either package configuration.

Moisture resistance testing (MRT) and package reliability tests (Table 3 ) have been completed with these two new package-stackable CSPs, using a 7.62 mm² package as the test vehicle. In MRT, 4× reflow at 260°C was used as the board assembly condition, including one additional reflow to stack the other package. We were particularly concerned about the possible occurrence of "popcorn phenomenon" (a well-known delamination effect caused by moisture absorption between the die attach material and the substrate). The cavity type of package has no die attach material for moisture entrapment, so no delamination was observed, even under MRT JEDEC Level 1 conditions. This performance enables the use of lead-free solder and also makes the package suitable for package stacking applications, where additional reflow steps may be required. For the no-cavity-type package, JEDEC Level 3 was confirmed.