X Architecture Becomes Mainstream

The concept behind X Architecture is not new — the ancient Greeks knew it well: A straight line is the shortest distance between two points. As Ketan Joshi, director of marketing, X Initiative, at Cadence Design Systems (San Jose), put it, "If you want to go from point a to b on two corners of a chip, using the orthogonal Manhattan design you'd normally go along vertical metal layers, then along the horizontal. If you went through a diagonal instead, it'd be a much shorter path — less wire (Fig. 1)." That is the idea behind X Architecture — X expressing the fact that 45° lines going in a "northeasterly" direction and others headed in a "northwesterly" direction appear to form an X.

1. X Architecture’s concept is that, with pervasive diagonal (45°) interconnect on Metal 4 and above, it becomes possible to produce a chip with 20% less interconnect and 30% fewer vias, while maintaining IP compatibility on Metal 1 to 3. This not only results in a more efficient chip, but also preserves existing infrastructure. (Source: Cadence Design Systems)

Diagonal routing enables designs with up to 20% less interconnect and 30% fewer vias. The concept maintains the lower metal layers (Metal 1 to 3) in Manhattan configuration — vertical and horizontal — to preserve compatibility with IP and standard cells, memory, or whatever designers may have previously created or are planning on. Metal 4 and 5 are turned 45° and 135°, respectively, providing eight degrees of freedom in routing — four degrees for the lower metal layers, making it possible to go north, south, east and west, as well as for the upper metal layers, which now can do so at a 45° angle. "In a Manhattan city grid," Joshi said, "streets go north, south, east and west. If we build elevated streets, which can go in northeast, northwest, southeast, southwest directions, you can travel more simply and efficiently between various points in the city."

Reduced interconnect provides considerable advantages. Most chips, starting at 180 and 130 nm, are interconnect-dominated. Performance is determined by the length — and number — of wires and their congestion. If 20% of that wiring is reduced, performance improves, the chip shrinks, and a real deployment is enhanced because there are more resources to route. Even in a congested Manhattan design, X can alleviate some of the congestion.

Fewer vias does not mean that double-cut vias or anything like that is being bypassed. It is still possible to have well-cut vias, but the number of jumps between metal layers has been reduced. Endemically, device manufacturers complain that vias cause manufacturability and yield issues, particularly as geometries shrink. Fewer jumps between the interconnect not only help with metal line resistivity, but also with yield.

In the Manhattan configuration, chip performance increases along with area (Fig. 2); however, if the design is implemented using X, the result will be a chip that is of equal area but higher performance, or of equal performance but smaller area. Some say X Architecture can give up to half a process node worth of advantage in performance and area. By implementing a design in 0.15 µm technology in X, it could perform like a 0.13 µm design.

2. Designs using X Architecture result in smaller, faster and better-yielding silicon than is possible with the traditional orthogonal Manhattan configuration. (Source: Cadence Design Systems)

Manufacturing X

X is a great idea for designers, but what about manufacturing? Is the supply chain already in place to support and implement this infrastructure?

In 2001, the X Initiative established its roadmap, forming a consortium to foster collaboration with IP vendors all the way to chip fabrication and wafer manufacturing. It established that confirmed manufacturability would be attained by 2002 — the mask-to-wafer supply chain. By 2003, this would be implemented in silicon, at least as test chips. By 2004, the first production chips were planned, and by 2005, there would be products using the architecture. Through an extraordinary atmosphere of cooperation and work performed in an open collaborative way by all members, the X Initiative has consistently delivered on all milestones, leading up to Toshiba's production chip in 2004.

The X Initiative is currently composed of 42 member companies.¹ It is a veritable supply chain of "Who's Who," from IP and design implementation to photomask and wafer manufacturing and inspection. Even on the foundry side, most of the major players are represented. Overall, the entire supply chain has come together behind the X Initiative. By 2002, already more than 80% of the manufacturing community was onboard as members.

At that time, multiple supply chains were established — 180 nm as well as 130 nm. The question then was, "Is it manufacturable?" Here, the focus was on mask and data preparation through wafer fabrication, and it involved all the leading-edge vendors. In mask writing, those doing raster as well as vector e-beam worked on the problem, and there were inspection and metrology providers and maskmakers, as well as leaders in lithography.

Jim Jordan, vice president of marketing and business development for BindKey (Santa Clara, Calif.), a DuPont Photomasks subsidiary, recalls this was one of those unusual cases where everything went smoothly and as expected. "Early on, DuPont Photomasks had talked about the mask writing aspect — we knew that sometimes angles are a concern; yet with the newer laser-writing tools and processes, as well as the new vector writing e-beam tools, we demonstrated that, compared to Manhattan geometries, we don't have any unique problems in creating photomasks. From a cost standpoint, we're really looking at the same production flow for what is a more efficient architecture — without any added supply chain costs!"

Initial lithography test work done by ASML and Nikon confirmed that, even with advanced lithography systems, fidelity and printability are equivalent to Manhattan's. "This was an area of concern when you have off-angle, non-orthogonal," Jordan said. "However, the X Initiative team crossed it without even a bump, demonstrating its feasibility. It certainly has been easier to make X Architecture work than it was to bring in copper, which had many more technology challenges than this. Essentially, we're just rotating the mask data 45°. When you think about it, we are not demanding that IC manufacturing tools and equipment perform something really way out of line. From a DuPont Photomasks perspective, the mask making has been straightforward — we're talking about the ability to write the mask, do metrology, and inspect, which are the major drivers of cost."

First silicon results took place in 2003. Along the Initiative's progression, it was demonstrated that the mask-to-wafer supply chain was not an issue. Typically, the next step in such a process is to refine the design rules and then use them on test chips to prove out certain fab lines. Cadence worked with STMicroelectronics (Geneva, Switzerland) and Applied Materials (Santa Clara, Calif.) to demonstrate that X Architecture design rules are comparable to Manhattan's. It was determined that it was still possible to go minimum width and spacing at these process nodes and effectively implement the design rules. After the design rules were established, Cadence worked with Toshiba to build a 90 nm functioning silicon chip to show that the architecture can be validated using actual designs. In 2004, Toshiba implemented a production digital TV chip using X. By mid-2004, they had wafers with close to 80% yield on those die. Now they are on track to mass produce this particular part by April 2005.

The chip was a 130 nm, 2.7 Mb gate design. Toshiba established two parallel projects to determine which gave the best performance: One worked on the same design using Manhattan, and the other used X. A few months into the design cycle, the Manhattan design had difficulties meeting the chip's performance course. Meanwhile, X had not only attained, but also exceeded, the performance required — the goal set was 162 MHz and X performed at 180 MHz, with a 10% smaller logic area. Toshiba then cancelled the Manhattan implementation and took X into production. Just by shifting Metal 4 and 5 layers, the Toshiba chip was 11% faster and 10% smaller, which is consistent with the theoretical work.

Toshiba's chip is an excellent example of co-existence between Manhattan and X. They took some of their Manhattan IP blocks and implemented sub-blocks using X. This is a classic example of how to use X: Some of the pre-built IP is leveraged, some new design infrastructure is built, and the pieces are assembled. Now nobody doubts whether X and Manhattan can coexist in the manufacturing and production environments.

The Toshiba experience also demonstrated that the complete design-to-silicon production flow is already in place. Not only from a design standpoint — the place-and-route extraction, all the specific steps typically followed in the implementation of the design — but also from the manufacturing side, the mask data preparation, OPC, wafers, etc. The device manufacturer concluded that all the steps were identical to those for Manhattan, and used standard tools for the production manufacturing of X, with the exception of place-and-route and extraction, which must be implemented differently.

When, by 2004, there was already production silicon from X, the attention shifted to yield. With PDF Solutions (San Jose), Cadence studied X's impact on chip yield. They used the same design with a Manhattan and an X implementation. The study demonstrated that, because X allowed for a die 10% smaller, the design could be implemented in a way that produced 12-13% more die in the same wafer area. Also, because of X's implementation in terms of area reduction, less wiring congestion, and fewer vias, net yield was also improved, resulting in 15-23% more good die per wafer. This is an example where, inherently, a new design architecture improves yield.

Hsinchu, Taiwan-based TSMC and UMC are also now on board. UMC is ready to accept X designs for fabrication at the 180, 150 and 130 nm nodes. TSMC has verified its 130 nm design rules and is now working on it with select customers. Overall, IDMs such as STMicroelectronics and Toshiba have tested the architecture through their fabs, while TSMC and UMC support the fabless side.

Today, there is considerable discussion about design for yield (DFY) — design must closely work with manufacturing to improve yield. Until now, most of the onus has been on manufacturing; on the mask and wafer manufacturing people improving the process to achieve better yield. Until X Architecture, few designers have demonstrated a significant way to improve yield.

X is a reality — it is manufacturable and production-proven; its performance, area and yield are all good. The question now is whether it is scalable — will it just be a 130, 90 nm story, or can it be used for 65 nm and beyond? Here Cadence worked with Applied Materials to produce a 65 nm test chip. They tested minimum width, minimum spacing structures using Applied's standard fabrication process (Fig. 3).

3. To explore the scalability of the X Architecture, earlier this year, Applied Materials fabricated the industry’s first 65 nm X test chip. X’s printability at 65 nm was excellent. A Canon AS2 scanner was used — 193 nm ArF, 0.7 NA, 2/3 annular illumination — attaining high pattern fidelity for X at multiple pitches. X and Manhattan wires in the same structure were patterned together, using existing flows and processes (same OPC, metal fill, mask flow and lithography). There was no special tuning, and the chips showed high pattern fidelity at elbows and double-bends. Electrical characteristics such as leakage current and resistivity in X were comparable to Manhattan’s. (Source: Applied Materials)

Mike Smayling, CTO of the Maydan Technology Center group at Applied Materials, explained that they took work done with 90 and 65 nm test chips to use with X. "We took structures designed by Cadence that are run at Applied as well at several IDMs and foundries, and looked at all aspects of manufacturing them. The news then (2004) was all good. We didn't find showstoppers and observed electrical data on the test structures that was comparable to that on same-size structures with a Manhattan layout. We ran everything through the design flow without problems in the layout, the OPC, or the mask making. There were minor concerns, such as whether the CD-SEM can measure non-orthogonal lines, but software revisions enabled our tools to perform measurements at any angle."

Smayling went on to say that having all these pieces already in place as they began building these structures was a welcome change from other technologies. "Very few changes were needed to do X," he said. "We'd been concerned about problems with metrology, inspection and perhaps maskmaking. They all turned out to be non-issues for our standard tool set."

Applied continues efforts in X with different partners. They are working on 65 nm test chips, which will include X Architecture structures. These structures will be targeted for an early look at 45 nm lines and spaces. As far as X is concerned, it seems everyone is following an evolutionary — not revolutionary — trail, and no surprises are expected. "One thing we're doing at 65 nm is using our Alta 4700 laser writer to do the masks," Smayling said. "The nice thing about X is that it doesn't introduce new materials or limit how materials are used on the wafer." There is no doubt that X is as scalable as Manhattan at the 65 nm node, using available standard techniques.

This is the year of first X products. Designers are seriously considering the architecture for their future implementations, and we will see products using it, as well as member companies putting out their solutions for implementing the architecture. First products will most likely be targeted at consumers. The architecture is applicable to the entire spectrum of markets. There is a craving in the consumer space to get X's area reduction benefits. In the wireless arena, the area and power reduction X also affords is attractive.

Because interconnect is the main benefit obtained with X Architecture, it is applicable to a certain class of designs, but not to others. For example, if an IDM's designs are 90% memory and it only has a few logic blocks, although the logic might slightly benefit from X, it would not have a sufficiently significant effect for the IDM to switch designs. Anywhere where logic implementation is a bottleneck in terms of performance and area, X will help.

In the design software infrastructure, the two main areas where new technology must be developed is in routing (because obviously new ways of routing the chips are needed), as well as placement, because now there are new routing resources to take advantage of by shifting the placement accordingly. The second area is extraction. Because there are now diagonal routes, it becomes necessary to be able to extract the appropriate parasitics. On the EDA side, most EDA technologies are quite similar, whether one considers OPC or even DRC/LVS rules. All the existing commercially available technologies and tools can be used with X.

There is no doubt that the X Architecture is ready for primetime. Through the X Initiative, industry giants have expended considerable effort to find deficiencies and weaknesses, and the evaluation that has resulted has been convincing. Now the issue will probably be how to implement X Architecture efficiently with CAD tools and make it as effortless for design as it is for manufacturing. Cadence and other X Initiative members are certainly committed to making it happen.

Author's Note: There appears to be every indication that X Architecture is not only an unmitigated success, but can be mainstreamed into production with a minimum of economic pain, insofar as capital equipment is concerned. Strangely enough, however, a majority of the X Initiative members declined to be interviewed for this article. One can only speculate that it may be likely that a major announcement may be pending, which might see the light of day by the time you read this article.