3-D Integration Enables 1 Gb Memory

Matrix Semiconductor (Santa Clara, Calif.) has developed what it says is the world's smallest 1 Gb silicon memory at 31 mm². The development was largely made possible by stacking the memory cells on top of one another, rather than spreading them out across the die in a planar fashion. Up to four cells are stacked, giving a 4× higher density than a planar design (Figs. 1 and 2). Siva Sivaram, chief operating officer at Matrix, noted that this is not a packaging technology done by wafer bonding, for example, but a monolithic device. "It comes out of the fab as a fully functional IC like everything else, except that it has active devices above the substrate. We take a standard CMOS wafer, process CMOS like you normally do, and then start building on top of it multiple layers of polysilicon-based devices," he said.

Sivaram noted that it's possible to get almost 900 of the 1 Gb die on a 200 mm wafer, using relatively old technology. "That's a big deal. If you look at flash today, they are all pushing the lithography. We are able to achieve very high densities, very small die size, but still staying back on relatively old-generation technology. We were able to achieve this in a 0.18 µm-generation fab, meaning the lithography tools are still 248 nm, for four active layers above the substrate," Sivaram said. "We are still in the stone age with respect to lithography tools."

First, Matrix uses a standard 0.15 µm CMOS process for the logic that will drive the memory and interface functions. Above the CMOS, tungsten routing layers provide the interconnect wiring. Next, the polysilicon memory layers are created. Finally, an aluminum top metal is laid down for power and ground distribution.

To create the memory array, a layer of tungsten is deposited. This layer is patterned into individual lines that serve as the wordlines for the first memory layer. Next, the anode terminal of the diode is created by depositing and doping a layer of polysilicon. Photolithography and etch processes are used to create the diode's cylindrical profile, then an insulating oxide is deposited to fill the area between the diodes. A CMP step polishes the entire area flat to allow additional layers to be added. After an ion implant step to create the cathode terminal, a very thin antifuse is grown on top of the diode. Finally, tungsten wires are again created to serve as the memory layer's bitlines. After depositing an insulating oxide over the bit lines, the entire process is repeated to create the four-layer memory stack.

1. This cross-section of a Matrix memory shows how the four layers of memory cells are built on top of tungsten routing layers and CMOS substrate.

Matrix is also using a unique segmented wordline architecture, for which the company recently received its 100th patent. This approach minimizes the effect of non-memory logic circuitry on silicon utilization. In traditional memory designs, the amount of silicon not used in the memory array lowers the overall manufacturing efficiency of the memory chip. Sivaram said the 3-D approach alleviates this problem by building the memory array on top of the logic circuitry. "The substrate CMOS is free for us to do anything we want," Sivaram said. "The charge pumps, the x-decoders, y-decoders, sense amps — they are all sitting underneath the memory."

The means array efficiency is high, even in very small die. Also, the segmented wordline architecture results in more efficient use of silicon, reducing the die's area by nearly 25%. "If you go back into standard memory design, you go to smaller densities, the array efficiency gets worse because you need the same scribe line, the same pad and the same I/Os, and the available memory goes down," Sivaram noted.

2. A close-up view of the memory cells.

By the end of 2005, Matrix will have applied these technologies across all of the memory capacities it currently offers (128, 256 and 512 Mb), as well as the new 1 Gb 3-D memory. Samples of these new products are available this quarter, and will be shipping in volume to customers in Q3 of 2005. "Last year, we launched 0.15 µm devices and shipped over 3 million units. Now, the third generation is coming up. The third generation has a whole slew of densities, including 128 Mb, 256 Mb, 512 Mb and 1Gb," Sivaram said.

For additional information on emerging technologies, go to www.semiconductor.net/emerging.