Multilayer Thin-Film Technology for On- and Off-Chip RF System Integration

As wireless communication devices become more abundant in numbers and variety, high-density system integration is becoming an increasingly important requirement. High-density integration of RF radio devices not only requires integration of active devices (RF system-on-a-chip [RF-SoC]), it also requires the integration of a large number of passive devices, such as transmission lines, resistors, capacitors and inductors, as well as functional blocks, such as filters and baluns. To reduce system size and cost, a higher degree of miniaturization is required. These components do not scale as well as active IC technology, making it difficult to integrate all these devices on-chip. Therefore, a proper portioning of the RF system is required. The active devices may be integrated in one or two SoC devices, and the external passive devices should be integrated in the SoC package, effectively realizing an RF system-in-package (RF-SiP, Fig. 1 ).

A key enabling technology for the realization of these RF-SiP "interposer" substrates with integrated passives is the multilayer thin-film technology — as used for wafer-level packaging (WLP) — of device wafers (redistribution and bumping). A key feature of this technology is the use of photolithographic technology for the definition of the various passive circuit components, resulting in a high degree in miniaturization and high patterning accuracy, with tolerances in the micron and submicron ranges. This results in excellent circuit repeatability and predictability — key ingredients for the realization of first-time-right and high-manufacturing-yield devices.

As transistor dimensions scale down and CMOS and SiGe are increasingly replacing GaAs for microwave and millimeter-wave applications, circuit performance becomes increasingly determined by the on-chip passive component quality. However, in the attempt to keep pace with this evolution, thinner on-chip metals and dielectrics have a troubling effect on the Q factor of on-chip passives. A cost-effective and attractive solution is to realize on-chip inductors using thin-film WLP techniques, similar to those used for realizing the RF-SiP interposer substrates.

1. Approaches to RF-SiP include an RF system consisting of several ICs and many discrete components (top); SoC integration of the active devices, use of “above-IC” RF WLP passives and integration of passives in the interposer board (middle); or further integration of RF MEMS devices in the interposer board (bottom).

Multilayer thin-film technology

The key features of a multilayer thin-film technology are the use of wafer-like process steps and photolithography. The infrastructure for this technology was developed for WLP or silicon back-end-of-line (BEOL) processing. High-volume manufacturing equipment with automatic handling is available for the common silicon wafer sizes.

The basic elements of this technology are a thin-film, high-density metallization technology and a thin-film dielectric deposition technique, capable of realizing very small via holes in the isolation layers to allow for high-density interconnects between the different layers in the structure.

Thin-film technology is well suited for the integration and miniaturization of passive components. Complex materials can be deposited with high repeatability to form quality resistor or capacitor layers. The thin-film lithography assures a high dimensional accuracy, enabling small tolerances and increased miniaturization, therefore avoiding the need for the "trimming" of resistor or capacitor values. The electroplated copper lines, described above, are ideally suited for realizing high-quality inductors, particularly those required for high-frequency applications.

Thin-film WLP technology, described above, can be used to realize an interconnect substrate technology with integrated passive components. An example of an RF-SiP buildup topology, developed at IMEC, is shown in Figures 2 and 3 .

2. Schematic cross-section of an RF-SiP interposer substrate technology with embedded passive components.

3. RF-SiP interposer substrate technology with embedded passive components on a high-resistivity silicon substrate.

4. This 7 GHz Wilkinson power splitter, integrated on a high-resistance silicon substrate, shows RF functions integrated in the RF interposer. Size is 1.65 × 1.05 mm2.

'Above-IC' RF-SoC

A feature of RF front-end ICs is the relatively large area occupied by on-chip inductors. The large size of these inductors is caused by the physical limitations of scaling inductors while maintaining performance (Q factor). Realizing these inductors on the RF-SiP interposer substrate, as described above, is generally not an option due to interconnect parasitics, even for a small flip-chip bump, which would degrade the performance improvement gained from using high-Q off-chip inductors. However, integrated passives technologies can also be applied directly on the device wafer or "above-IC."

For many high-frequency RF ICs, the poor quality factors of regular on-chip inductors are a limiting feature. This is because of the relatively high sheet resistance of the on-chip metallization and the losses in the semiconducting silicon substrate. By placing the spiral inductor in the thin-film layer — "above-IC" — the distance between the spiral and the lost substrate is greatly increased. By using a thicker, electroplated copper conductor, a much lower track resistance is obtained.

5. A high-Q, 10 µm thick copper inductor processed on top of a 10 µV-cm CMOS wafer.

The post-processing is compatible with both copper and aluminum on the back end. The technology is cost-effective and consumes no additional silicon real estate. Measurements performed on MOS transistors and back-end interconnects show no important performance shifts after post-processing. The WLP inductors have increased performance and resonance frequency, as compared to back-end versions, enabling the design of high-performance, low-power circuits, such as VCOs.

IMEC applied this technology to realize a 5 GHz and 15 GHz low-power VCO in 90 nm CMOS. The 5 GHz and 15 GHz VCOs use a 3 nH and a 0.6 nH WLP inductor, respectively, without ground shielding, resulting in a differential Q factor of 40 and 55, respectively. The 5 GHz and 15 GHz VCOs show a low core power consumption of 0.33 mW and 2.76 mW, a phase noise of -115 and -105 dBc/Hz (at 1 MHz offset) and a tuning range of 148 MHz and 469 MHz, respectively. For comparison, a 6.3 GHz 90 nm VCO using a back-end inductor with patterned ground shield has a core power consumption of 5.9 mW with a phase noise of -118 dBc/Hz at 1 MHz.

6. Differential 1.6 nH “above-IC” inductors integrated on a 10 µV-cm CMOS wafer. The inductors were made with two turns and a line thickness of 10 µm, line spacing of 10 µm, linewidths of 10-40 µm, and inner diameters of 250 µm.

Conclusion

Multilayer thin-film WLP technology with integrated passives can be applied both on active wafers (RF-SoC) and on intermediate glass or high-resistivity silicon substrates (RF-SiP). The results prove that thin-film technology allows integrating high-Q passives for wireless telecommunication applications covering a very broad frequency range, from the 1-5 GHz mobile phone standards up to 77 GHz automotive radar.