Wire-Loop Shaping in Multi-Tier Packages

Current multi-tier devices in production consist of triple-tier bond-pad layouts (Fig. 1 ), and quad-tier die are on the horizon. Chipmakers are finding that the multi-tier layout is more feasible from a wire-bonding standpoint than continuing to reduce pad pitches, since a triple tier of 60 µm pitched bond pads can have an effective 20 µm pitch. The additional silicon required to accommodate more bond pads is a worthwhile trade-off for robustness in the wire-bonding process. Another advantage of the multi-tier package is that conventional materials, with respect to capillaries and wire, can be used to assemble these packages. The fragility of ultrafine-pitch capillaries and wire is not well suited for production.

The emergence of multi-tier packages has also created new challenges in wire-loop shaping.¹ The use of multiple layers of wires in a single device is difficult because the loop shapes must have sufficient clearance to avoid wire shorting while limiting the overall height of the package. To achieve these goals, the lower layers of wires must be kept as low as possible and the upper layers of wires must employ higher loop heights and maintain longer flat lengths to traverse the lower layers.

1. Two examples of triple-tier bond-pad layouts.

Multi-tier device layout

Some multi-tier packages consist of triple-tier die attached to five layers of leads on the substrate. The first three tiers on the substrate are commonly the power and ground rings, and the last two tiers are for I/O assignments. These multi-tier device layouts, with their increased number of wires, make it difficult to create sufficient clearance between wires, and they complicate wire-bonder process-program setup. Figure 2 shows three substrate layers of a multi-tier device.

2. Three levels of second bond locations on a multi-tier device.

One method for avoiding wire shorting on the power and ground wires is to stagger the loop heights. However, in some device layouts, it may be possible to keep the loop heights the same by positioning the second bonds to maximize the space between wires. Keeping the first few layers of wires at the same loop height is crucial for minimizing the overall package height. On the other hand, staggering the loop heights is advantageous because it can prevent wire shorts when the die placement shifts with respect to the second bond locations. Sophisticated wire-bonder application software can also help minimize the effects of die shifting by utilizing reference system and wire-to-wire dependencies to maintain wire spacing from package to package.

Along with the die-placement repeatability concern, wire bonder to wire bonder portability and variation in bonding materials create the need for increased clearance between wire-loop layers. Typical horizontal clearance can be as small as 1 wire diameter (~1 mil), while vertical clearance may be as much as 3 mils. The loop heights may range from 3 to 6 mils for the lower wire layers, 9 to 12 mils for the middle wire layers, and 15 to 18 mils for the upper wire layers. Wires that exceed the maximum allowable loop height will cause defects because of exposed wires after mold. Another issue that affects wire clearance is the close proximity of the substrate layers. Wire loops attached to outer layers must clear the inner layers by 1 or 2 wire diameters to avoid shorts between the wire and substrate.

Other multi-tier device layout issues include wires attached to the same lead and short wires. Wire clearance becomes a problem when wires are attached to the same lead, because the top wire can interfere with the bottom wire during the top wire's approach into second bond. If possible, it is beneficial to keep the second bond locations staggered on the same lead. When bonding short wires, inconsistent wire payout during the shaping process is magnified by the resulting loop. At one extreme, excess wire payout creates loops that are too tall and eliminate the clearance between the next layer of wires. Conversely, the loop can become too tight and decrease the clearance over the die edge or even break. This loop-height variation in short wires is exacerbated by the changing wire length and bonding direction that are associated with radial bond programs.

There are several loop-shape options for minimizing the loop height of the lower-layer wires, and there are trade-offs between using each shape. The traditional loop shape is not well suited for ultralow-loop-height applications because it is susceptible to neck damage.

Modifying the shaping process to exclude the reverse motion² can provide some relief. In another modification, the reverse motion is enhanced to crimp the wire on top of the first bond to create a lower starting point for the subsequent looping motions. This loop allows ultralow loop heights, but the additional shaping motions decrease wire-bonder productivity. This loop also eliminates neck damage concerns, although pull strength near first bond is sacrificed. To increase pull strength, the crimping reverse motion can be made less aggressively; however, the ultralow-loop-height capability is slightly compromised. Another loop-shape option is the reverse-bonded or standoff stitch bond (SSB) loop.

The SSB loop is highly unlikely to be used in production because it is the slowest process. Also, looping back onto the die surface creates clearance problems with the die edge and upper-layer wires. To address the die-edge clearance problem, the improved bumping technique provides more support to raise the loop into the bump on the bond pad.

The SSB loop is not ideal for lower-layer wires because its shape tends to include higher loop heights out near second bond. This extra height makes it difficult for upper-layer wires to create sufficient clearance to avoid wire shorting. A benefit to using this profile would be that it provides more clearance for the upper-layer wires above the bond pad.

The upper-layer wires require a wire loop that can maintain a higher loop height further away from the ball bond so that there is sufficient clearance over the wires below. The traditional loop shape is preferred because it will provide the fastest process time.

However, move advanced loop shapes are sometimes needed to provide more loop-height clearance further away from first bond. These advanced loop shapes, shown in Figures 3 and 4 , create long, flat lengths to maintain the higher loop height, and then create a large kink to bring the wire sharply into the second bond location. Creating the extreme loop-height clearance increases process time and leads to performance issues, such as sway, decreased stability and inconsistency.

3. Advanced loop shape with sharper last kink.

4. Advanced loop shape with smoother last kink.

The upper-layer wires must also create loop-height clearance at the first bond location. This extra height above the bonded ball can cause wire leaning, which may be alleviated by using three reverse motions.

The limited wire clearance in multi-tier packages is extremely critical during the molding process. The flow of mold compound can sweep the wires and cause wire shorting. One method for guarding against mold sweep is to kink the wires laterally during the loop-shaping process. The lateral kink is done in the direction of mold flow to make the wire more resistant to mold sweep.

Another method to counter mold sweep is NoSweep, an epoxy encapsulant. NoSweep is dispensed onto the device immediately after wire bonding, and then cured to lock the wires into place. Figure 5 shows a multi-tier device using a single ring of NoSweep to immobilize the wires.

5. Multi-tier device with NoSweep.

In addition, NoSweep has been shown to separate shorted wires. It is formulated so that the spherical filler size is much smaller than the space left between the wires. The size distribution of the silica filler allows small particles into the narrow space between wire loops, thereby driving the wires apart.

To ease the looping process challenges, several advancements have been made in bonding materials. Gold wire manufacturers³ are studying the chemistry, heat-affected zone, hardness, spring-back height and elastic energy effects of wire to accommodate multi-tier packaging. Typically, wires used for low and high loop heights have been engineered separately for various packages. However, the multi-tier package requires one wire to be used for both the low and high loops that range from 3 to 18 mils high. These new wires must not be susceptible to neck damage, and they must be specified to meet the requirements of short and long wires. For the long loops of the outer layers, the bonding wire must be capable of maintaining long, flat lengths without sagging or swaying. Reducing wire sway in these new wires can also lessen the failures seen after molding.

Capillary design engineers are studying the effects of changes in key dimensions and geometry tolerances to determine which features significantly influence the loop-shaping process. This type of study involves characterizing changes in loop height, overall loop shape, and wire sway to gauge the effect of each capillary feature. Engineers are also determining the significance of capillary design on loop-height differences associated with bonding direction, which are more prevalent in the challenging loop-shaping processes of multi-tier packages.

Wafer probe manufacturers have been using finite element analysis (FEA) to study the effects of probe geometry more closely. Stress, stress areas, forces and geometry effects are typically studied in the FEA. Figure 6 shows the output for an FEA model of the forces applied to a probe tip under normal working conditions. These studies have established design goals for dimensions that are critical for maximizing probe life and scrub length.

6. Finite element analysis model of forces applied to a probe tip.

The large number of variables in probe manufacturing, along with variables in customer wafers, leads to a difference of opinion over wafer-testing methods. Therefore, probe card designers must account for the test engineers who want to break through the heavy oxides and those who want very controlled breaking of glass and depth of scrub.

The flexibility of wire-bonding technologies enables process solutions that are critical to the success of multi-tier packaging. Continuous process improvements in the wire bonder, capillary, bonding wire and probe are enabling device assembly. Innovations in the wire-loop shaping process are also critical for driving the roadmap for this new package design. The challenging wire shapes require ultralow and high loop heights that can be formed consistently to maintain sufficient clearance. To meet these demands, existing loop shapes are modified or new shapes are created. The loop-shaping process, along with the NoSweep epoxy encapsulant, is also being used to address potential yield loss from mold sweep. Wire bonding continues to offer a viable low-cost option to flip-chip for assembling area array devices.