Recorded live at Sematech’s Litho Forum, this panel discusses the hurdles facing EUV, double patterning, high-index immersion, nanoimprint and e-beam maskless lithography technologies. As it turns out, they have much in common.

Andreas J. Heinrich and Markus Ternes explain their development work aimed at measuring the force that is required to move an atom. Their successful effort has opened the possibility of building nanotech structures by starting with a single atom.

Peter Woditsch, CEO of Deutsche Solar AG (Freiberg, Germany), talks about the company’s solar cell manufacturing operations. He describes how a Bridgman crystal growing method is used to produce the polycrystalline “bricks” of silicon that are turned in to wafers with a wire saw, and the other steps that result in solar cell modules.

Senior Editor Alexander E. Braun moderates this roundtable session, in which experts give their experiences on overcoming the hurdles involved in the transfer of technology from the various R&D sites across academia to the industry sector — where the realities of developing a concept into a manufacturable product take place.

Mike Lercel, lithography director at Sematech and also U.S. chair of the ITRS lithography working group, highlights the latest updates to the ITRS Lithography chapter, including changes in potential solutions and tighter CDU and overlay requirements.

Mark Melliar-Smith, CEO of Molecular Imprints Inc. (MII, Austin, Texas), explains why he’s more optimistic than ever about nanoimprint lithography and its capabilities, particularly for high-density memory.

As a follow-up from the EUVL Symposium in Sapporo, Japan, Kurt Ronse, IMEC’s director of lithography, talks about the source upgrades expected on the EUV alpha demo tool at IMEC, plus a variety of other issues surrounding EUV lithography’s development.

Doug Grose, senior vp of manufacturing and supply chain management at AMD, discusses his perspectives on the wafer size debate, bulk silicon vs. SOI, manufacturing productivity, and more.

Serge Biesemans, department director of CMOS Device Technology Research at IMEC, talks about the positive effects on variability and performance associated with a move to finFETs, especially for SRAMs. Embedded SiC, for enhanced nFET mobility, is also moving closer to production.