Copper/Low-k Challenges for 45 and 32 nm

The semiconductor industry is at a state where the fundamental scaling laws are starting to challenge the extendibility of copper interconnects. These include electromigration (EM) caused by the surface interface, electron scattering based on the wavelength of the electrons relative to the size of the interconnects, and also fundamental limits on dielectric, electrical and mechanical strength. These were the main conclusions from a recent webcast hosted by Semiconductor International, where IBM’s Dan Edelstein, IMEC’s Rudi Cartuyvels, Sematech’s Sitaram Arkalgud, Micron’s Gurtej Sandhu, and Albany NanoTech’s Jim Ryan discussed interconnect challenges for upcoming logic and memory devices.

The good news, says Edelstein, is that these challenges have solutions, but he cautions that “the manufacturability of these solutions is not presently at the level that would be acceptable for high-volume, high-yield production. There needs to be significant industry attention on some of these solutions to bring them up to those levels, if at all possible.”

The industry is now routinely manufacturing chips as large as 2 cm on a side or even slightly larger with 10 levels of copper wiring; the total can exceed one to two miles of wire. “The complexity is tremendous, and all of this is necessary just to connect one layer of transistors, which have even smaller features and can exceed a billion in count on a chip.”

One of the major problems facing chipmakers is that, as copper interconnects are scaled, EM becomes more of a problem. “As the ratio of atoms near the surface relative to the bulk increases, the lifetime goes down and that is because the top surface of the interconnect is the fast diffusion path. We’re now at a point where the fundamental scaling is crossing over the needs of the technology, so we’re losing 50% of our electromigration lifetime every generation.” The most promising solution is a selective electroless metal capping layer such as CoWP, which would lock the copper atoms in place. Selective processes are notoriously tricky, though, in addition to being common sources of shorts and leakage.

A related problem is that EM is worse for lines that do not have a “bamboo” crystallization structure. Weak interfaces at the copper-liner interface or grain boundaries become an easy path for EM.

Yet another challenge relates to how the liner and seed layers that surround the copper damascene trench must also scale in order to fabricate the lines as they shrink. So far, for six generations, physical vapor deposition (PVD) has been able to provide the step coverage that is needed, but it’s unclear if continued advances in PVD are possible. “There are alternative deposition processes that do have good step coverage, and there are attempts to develop these to replace that TaN/Ta barrier and the copper seed layer,” Edelstein said. “The step coverage is there, but there are definitely risks with these processes.”

In terms of low-k dielectrics, for high-performance chips at 90 nm, most companies have implemented around a 3.0 dielectric constant, predominately using organosilicate glass (SiCOH). “We’ve extended this in the 65 nm node with a slight decrease in dielectric constant from 3.0 to 2.7 simply by changing the deposition recipe,” Edelstein said. “We were able to go to a weaker material without losing reliability. More recently, we’ve extended this to a 2.4 porous dielectric using the same disciplines and techniques and a slightly different precursor setup, but the same tooling.”

Another presenter looked at what might be required beyond what is now conventional copper and low-k approaches. “Since we’re running into many scaling issues, people start thinking about what’s next beyond copper and low-k,” Cartuyvels noted. “We’ve looked in a benchmarking study at other alternatives that might be closer to production. What could potential technologies bring? Let’s just consider interconnect, push signal from one site to another and compare interconnect options, and analyze some metrics. One metric we analyzed was the energy required to transport that bit from one point to another, and the speed at which you can do that. The solution might be to not scale Cu/low-k, especially for the global wires to make sure you have enough signal speed. We also compared that with other options like 3-D interconnects, and LC types of interconnects, which operate in LC regime. ... A final option we considered was going to optical interconnects.”

The result is shown in the Figure , which plots energy delay product vs. bandwidth density for 1 cm long interconnects. “You would like to be in the lower-right corner where you’re extremely fast with extremely low power consumption,” Cartuyvels said. “What you see is that there is not one solution that does it all.”

Energy delay vs. bandwidth density for various types of interconnect strategies. (Source: IMEC)

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