Transcript: Sematech Director Discusses High-k/Metal Gate Progress

Senior Editor Alexander Braun with Raj Jammy, IBM assignee to Sematech as director of the Front End Processes Division, at the IEEE/Applied Materials Symposium on High-k/Metal Gates Oct. 26 in San Jose

Alexander E. Braun, Senior Editor -- Semiconductor International, 10/31/2006

Listen to the audio interview (Runtime: 6:18)
 
Braun: This is Alexander Braun, senior editor of Semiconductor International magazine, reporting from Silicon Valley at the symposium on high-k/metal gates, co-sponsored by the Electron Device chapter of the IEEE and Applied Materials. I have with me Dr. Raj Jammy, who is director of front-end processes and IBM assignee with Sematech.
 
Dr. Jammy, you did a presentation on the feasibility, scalability and manufacturability of high-k/metal gates. Can you tell us a little bit of how you see the lay of the land these days?
 
Jammy: Certainly. First of all, hello, Alex. Thank you for having this interview with me.
 
A lot of work has been done on high-k/metal gates, and trying to make devices that work, for more than seven, eight, almost 10 years, actually. And I think all that hard work is slowly coming to fruition now. And people do know the kind of dielectrics that can be used, or should not be used, and how to manipulate these dielectrics to some extent. And also what kind of metal gates should be used, and how can we harness these metal gates so that we can make devices that are practical and manufacturable. And we’re not completely there yet. We’re getting there; we’re very close to implementation.

Braun: So, you mentioned that scaling has stopped for gate dielectric, for all intents and purposes. What options are we looking at now?

Jammy: Right. This was in reference to SiO₂ or silicon oxide or silicon oxynitride gates. So those gates with polysilicon electrodes have stopped scaling. So once these dielectric stacks or gate stacks have stopped scaling, we really had no option left. But for performance enhancement, people continue to use new ideas, like mobility enhancement. And therefore, they continue the scaling that the industry is so used to. But in some point in time we have to get back to the dielectric and try to see how we can continue to scale the dielectric also – part of it for the improvement in the coupling that we achieve at the channel, and therefore drive more current; but also the key part of it is reducing the leakage that comes from the gate dielectric.

Braun: How scalable will high-k be? What will be the mobility questions that we’ll be facing?

Jammy: High-k dielectrics in general have exhibited a degradation in mobility, and this is primarily because of two main factors – one being that of charge that gets incorporated in the high-k dielectrics. They’re metal oxides, and the oxidation states are not very well known, as the second speaker was presenting today. And also the kind of impurities that go into metal oxides are also not well understood. So charge states and charge trapping that comes from that, and therefore the mobility degradation that comes from such charges is one key factor.

Another factor is that the bonding and the bond strength that the metal oxide systems have is very different from that of SiO₂ bonds. SiO₂ bonds are much more rigid, so the vibration states that they have have much higher energies, and they don’t necessarily couple with what happens in the silicon channel. On the other hand, the softer energy states that the higher-k dielectric materials have couple more easily with the carriers that are going between the source and the drain, and therefore there’s a degradation in mobility.

Braun: What are some of the lith considerations that we’re facing? What’s the lay of the land for lithography?

Jammy: Lithography from a gate dielectric perspective, from a gate stack perspective?

Braun: Yes.

Jammy: One thing that I did not touch upon today in my talk, but one thing that is very important is, as we continue to scale the gate length, as we call it, which is really the distance between the edge of the source and the edge of the drain, and we try to keep this gate length as small as possible, and this scaling has been happening quite aggressively for generations now, and it’s typically been – in the most aggressive terms it has been about 50% of the drawn length. When we say a certain generation technology, the gate length has been about half of that. But in the recent past, even that scaling has sort of slowed down. And it’s creeping about the 60% or close to 60% mark. And people try to reduce that, but there are a couple of things that affect that. One, of course, is can you have lithography control, and can you repeat such highly scaled gate length across the entire wafer and across the entire devices? And the other part, of course, is what kind of short-channel effects do you have to contend with when you bring the sources and drain edges very close to each other?

Braun: Last question. You said something to the effect that the test methodology for silicon dioxide may have to be completely rethought for high-k. What’s the situation there?

Jammy: There is substantial learning since we started working on high-k dielectric materials. Many of the ideas and many of the thoughts that we had in SiO₂ are not necessarily applicable to high-k dielectrics. And high-k dielectrics – especially with metal gates – behave completely differently in failure modes, breakdown modes, and also in terms of how they trap charges, and what impurities cause what kind of trapping and de-trapping mechanisms. So how we test them is strongly dependent upon a good understanding of these defect states, first of all, and then we have to design test methodologies to compensate for those, so that we can get a true extraction of that lifetime, the device lifetime, and their behavior and their performing conditions.

Braun: Great. Well, thank you very much, Dr. Jammy, for your time. And I’m sure that our listeners will find this of great interest.

Jammy: Thank you, Alexander.