DFT puzzle comes together

Design-for-test (DFT) tools are smoothing the way toward complex device designs that are readily testable on economical ATE systems. Vendors of DFT and built-in-self-test (BIST) tools have been polishing their offerings so they easily fit together in the design flow—from behavioral-level design descriptions to fabricated silicon.

Those tools include the venerable DFT scan insertion, which lets ATE systems probe the operations of logic cells buried deep within an ASIC, albeit at less than rated speed. The tools also include embedded BIST structures that can exercise internal circuitry at speed, although without the deterministic fault coverage of pure scan. Rounding out the testability-enhancement offerings are automatic test-pattern generators (ATPG) as well as BIST-related vectorless tools that skip the ATPG stage altogether, providing tester-ready output in an ATE system's native mode.

Effective DFT implementations aren't the domain of electronic-design-automation (EDA) software vendors alone. In many cases, BIST and DFT vendors receive help from ATE vendors in smoothing the design-to-test transition. This assistance includes the adaptation of ATE operating systems to interface readily with EDA firms' ATPG or vectorless outputs. EDA and ATE vendors are also cooperating to develop "tester-aware" EDA tools and "EDA-aware" ATE systems. The result is a bidirectional design-to-test link that can help designers diagnose chips based on ATE results and that can help test engineers develop effective test programs based on EDA outputs.

Analog BIST functions will ultimately become invaluable additions to design and test engineers' toolboxes, but as yet, analog pieces don't mesh seamlessly with IC design flows, as do the digital pieces. Consequently, the seamless integration of design and test appears mostly in the digital realm. The analog and mixed-signal arena doesn't include the automated synthesis and optimization tools of the digital arena, as some panelists reported at the June 2001 Design Automation Conference (Ref. 1). Panelists noted that the current "design, simulate, adjust, repeat" process of analog circuit development relies heavily on designer experience, which cannot be captured by current automated tools.

An as-yet unbridged gap lies between the analog-simulation world of Spice and the DFT-friendly logic-simulation world of Verilog and VHDL hardware-description languages (HDLs). Analog extensions to Verilog hold some promise for bridging this gap, and emerging top-down analog synthesis techniques may provide the necessary structures for seamless integration of analog BIST tools, but no one will venture a construction timetable.

For now, there's no analog counterpart to scan insertion, and the BIST functions available for mixed-signal blocks (such as data converters, voltage-controlled oscillators, and phase-locked loops) employ digital input and output signals to exercise and evaluate analog portions of the mixed-signal circuit blocks. The IEEE 1149.4 boundary-scan standard with analog extensions defines an infrastructure for a true analog pathway, but the commercial IEEE 1149.4 implementations, from LogicVision and National Semiconductor, that have emerged so far have been aimed at PCB test, not at test of internal device analog nodes.

Boundary-scan BIST vendors other than Logic-Vision have focused on their digital IEEE 1149.1-based offerings. For example, Greg Aldrich, product marketing manager at Mentor Graphics, says his firm is enhancing its BSDArchitect as a pathway for exercising multiple memory and logic BIST controllers within multicore system-on-chip (SOC) devices.

So, true analog BIST, in which embedded testers generate analog test-stimulus signals or measure and evaluate analog outputs, remains at the R&D stage. David Hsu, director of marketing for test automation products at Synopsys, says his company is looking hard at analog DFT but that no road map for the technology currently exists. Customers, he says, do request that analog circuitry be isolated from DFT-enabled logic circuitry so functional ATE systems can readily test analog portions.

Gregg Lowe, senior vice president at Texas Instruments' high-performance analog business unit, sees that isolation extending to the chip boundaries—it makes no sense to implement digital functions within an analog process or vice versa, he says; it's better to pursue higher densities on all-digital or all-analog ICs and interface the two domains at the PCB level. He adds one caveat: It does make sense to combine the two in size-critical and power-critical mobile products.

That's not an insignificant market, yet DFT help here will continue to wait for the bridging of the Spice/HDL gap. David Stannard, product-marketing manager for the embedded-deterministic-test product group of Mentor Graphics' Design-for-Test division, concurs that analog BIST products aren't imminent, as analog BIST techniques remain primarily in the domain of universities. Interest in the topic is born out by several analog-DFT-related papers presented at this year's VLSI Test Symposium (April 28–May 2 in Monterey, CA), but the presenters overwhelmingly represented academia.

In contrast, vendors are progressing nicely on forging BIST and DFT products for use in commercial products. At the same symposium, presenters described how they employed 80-MHz tester signals in conjunction with an on-chip clock controller circuit and Mentor Graphics automatic test-pattern generation technology to test 500-MHz Motorola PowerPC microprocessors at rated speed (Ref. 2).

Since my last extensive report on DFT (Ref. 3), vendors of logic BIST tools have held their own. The basic building blocks remain the same: You'll find BIST tools for implementing RTL embedded-test structures in logic blocks and memory blocks from vendors including Genesys Testware, LogicVision, Mentor Graphics, SynTest Technologies, and Credence Systems' Integrated Measurement Systems (IMS) subsidiary (which has absorbed Fluence Technology). On the memory-BIST front, Virage Logic has implemented on-chip test as well as repair for memory blocks. IMS and LogicVision continue offering their BIST tools for mixed-signal devices such as ADCs, DACs, PLLs, and VCOs.

All of these tools are becoming easier to use, as vendors enhance their software to facilitate "what-if" engineering analysis and to establish transparent links with production ATE systems. Hau Lam, IMS product marketing manager, points out that the timing-analysis capability added to his firm's TestDeveloper software makes it easy to convert Cadence Design Systems' Verilog Value Change Dump files or ATPG outputs from Synopsys's TetraMAX or Mentor Graphics' FastScan and TestKompress tools to tester-readable formats.

The links with silicon foundries are smoother, too, according to Mike Kondrat, marketing vice president at IMS. He explains that Fluence Technology used to expend effort validating its BIST products on various manufacturers' silicon processes, but now BIST intellectual property (IP) is more readily compatible with silicon vendors' deep-submicron libraries.

The digital BIST tools that firms like Genesys Testware, IMS, LogicVision, Mentor Graphics, and Syntest offer fit smoothly within typical digital design flows, which begin with HDL behavioral descriptions. The BIST tools create on-chip embedded-test structures that initiate at-speed tests of internal logic or memory devices, transferring test-initiation and test-response information to an external test system over a few low-speed channels. Those channels in turn can interact within the scan chains engendered by scan-insertion tools from Cadence Design Systems, IMS, Mentor Graphics, Synopsys, and SynTest. (See Figure 1 in Ref. 2.) Of course, the implementation of DFT strategies can cause its own problems within a chip. Tools including Atrenta's Spyglass DFT can help to identify test-rule violations that otherwise would require time-consuming debug operations by test engineers.

ATPGs from IMS, Mentor Graphics, Synopsys, and SynTest Technologies use the completed scan designs to develop the test-vector sets that serve as input for test-program generation. Fault simulators from firms including Cadence, IMS, Mentor Graphics, and Provis determine whether the test coverage those vectors provide is adequate.

Next, tester-emulation and test-program-development tools from IMS facilitate test-program development. A BIST-enabled RTL design can undergo synthesis and scan insertion just as any RTL digital design can. The subsequent automatic-test-pattern-generation stage generates test patterns that initiate and monitor embedded-test operations, with results boiled down to stuck-at-one and stuck-at-zero conditions that an ATE system detects.

And while ATPGs generate vectors for exercising scanable devices, HDL test benches from firms including Diagonal Systems, Mentor Graphics, and Synapticad help develop functional vectors to test device functions that escape the attentions of even the best DFT approaches. The final step in the design-to-test process is the ATE system itself, and various ATE vendors are offering systems that cater to the needs of DFT-compliant and BIST-enabled designs. The new offerings include systems closely tailored to the DFT needs of specific device types as well as ones that focus on the needs of scan-design tests yet maintain sufficient flexibility to accommodate functional test vectors and mixed-signal tests.

Of course, scan chains aren't the only pathway to external testers. Embedded test blocks can communicate with the world outside the chip—that is, the ATE system—via a test-access mechanism (TAM) that mirrors the IEEE 1149.1 Test Access Port (TAP). LogicVision has implemented such an approach with its Embedded Test 4.0 (Figure 1), a tool compatible with hierarchical design tools that integrate BIST structures within SOC devices; it supports vectorless transfer of test data to ATE systems including Advantest's 66XX Series systems, Credence Systems' Duo and Quartet testers, and Teradyne's Catalyst systems. An ATE-independent interactive user interface lets you adjust any parameter or operational mode of any BIST structure embedded within the target DUT; once you've optimized test, you can establish go/no-go limits for high-volume production test. 

Figure 1. Able to support interactive IC debug, LogicVision's Embedded Test 4.0 includes a database that stores information on embedded-test structures and on target ATE systems. The combination supports BIST insertion as well as vectorless test-program development.

Synopsys has focused on test-modeling technology based on the proposed IEEE Core Test Language (CTL) standard—the P1450.6 extension (previously designated P1500) to the IEEE 1450 Standard Test Interface Language (STIL) standard (Ref. 4). The company has sought links with ATE makers as well as device makers.

Last October, Synopsys and Agilent Technologies demonstrated the porting of test patterns from Synopsys's TetraMAX ATPG directly to Agilent's 93000 SOC test system by way of Agilent's SmarTest PG (Program Generator) software. SmarTest PG replaces the scripts and manual procedures typically required to adapt design files for production test; it generates 93000-loadable program files tailored to the target tester's pattern-generation, timing, pin-configuration, and DC-level characteristics.

SmarTest PG is bidirectional, allowing it to communicate tester characteristics such as scan-chain and scan-buffer-memory limitations to TetraMAX in a CTL-compliant manner. That makes TetraMAX a "tester-aware" tool able to provide tester-specific rule checking; that rule checking, in turn, enables TetraMAX to provide a STIL-compliant output that the target 93000 tester can run.

The SmarTest PG-to-TetraMAX link grew out of a partnership between Synopsys and Agilent announced in March 2001. In March of this year, Synopsys also announced a two-year agreement with device vendor STMicroelectronics. Although descriptions of the techniques that might arise out of this agreement weren't available at press time, the companies did say they expect to use the CTL standard to speed device diagnostics and test-program development.

Figure 2. a) Design-rule checking in Synopsys's DFT Compiler identifies uncontrollable-clock and asynchronous-reset inputs to a bank of flip-flops. b) DFT Compiler's Autofix function adds the necessary components to correct the defects.

The goal of a core-test standard is to provide adequate test of a DUT's internal core components without burdening the external ATE system. Rudy Garcia, strategic marketing manager at Schlumberger, warns, however, that designers could negate some of the potential benefits if they don't take care when designing test collars—circuitry that implements test functions within cores. He sees a trend toward a minimal-transistor collar that can effectively test each core but preclude adequate test of the interconnect between cores, which would require an at-speed functional ATE system. Adding more functionality to the collar could minimize the need for external functional ATE, he says, but at the cost of additional transistor overhead in the collar.

Effective DFT strategies require the availability of compliant ATE systems, which first require large amounts of scan-buffer memory to store the vectors needed to test full-scan or partial-scan ICs. Mentor Graphics is one EDA vendor that decided not to wait on the ATE vendors. It took the first step and effectively increased the scan-buffer memory of existing ATE systems by compressing test-vector data tenfold or more (at the cost of some silicon overhead in the DUT).

Mentor Graphics' Stannard says that fivefold to tenfold reductions seem to be the most cost-effective level for most customers, although there are no engineering barriers to getting much higher reduction rates—at higher costs.

Not to be outdone, ATE companies are offering optimal DFT implementations that provide prodigious amounts of scan memory and that support an appropriate number of scan chains—be it a few deep chains (which can minimize DFT overhead on chip) or many shallow ones (which can speed test time). The goal of a DFT-focused ATE system is adequate performance at absolute minimal cost. Headline-making 3.2-GHz basic clock rates are out of the picture here. Top speeds on scan-ready systems are 200 MHz; thermal considerations keep typical production scan-test operations at 100 MHz and less.

Figure 3. Taking aim at microprocessor test, the DeFT system supports scan test while providing precise control of timing edges and stable, high-current power supplies. Courtesy of Schlumberger.

Figure 4. Although focused on structured scan testing, the Integra Flex is extendable to perform mixed-signal and functional logic tests. Courtesy of Teradyne.

G. Taylor Driggs, DFT group marketing manager at Teradyne, says his company tailored the Integra Flex to accommodate a variety of test approaches. In addition to accommodating analog instrumentation, the Integra Flex offers what Driggs calls a "sea of bits" approach to test-vector memory that can store functional as well as ATPG vectors in a variety of width and depth configurations. Integra Flex also offers what Driggs calls "floating clusters of clocks," which enable test engineers to apply different clock signals to each of a DUT's various clock domains.

Beyond scan testing, ATE firms are working to adapt their systems to test BIST-enabled devices. Advantest and Credence Systems have teamed up with LogicVision to earn their systems a "LogicVision Ready" label, which indicates that the system bearing the label can interface with LogicVision tools to generate the signals necessary to activate Logic-Vision embedded-test structures within DUTs. Vinod Agarwal, LogicVision CEO, estimates that ATE vendors might need to spend two to three engineer months to adapt their testers to a LogicVision-provided application programming interface and to integrate the resultant code within their testers' operating systems.

LogicVision's vectorless-test-data-transfer approach assumes that the DUT is a fully BIST-enabled chip whose BIST functionality provides sufficient fault coverage. Steve Morris, president of Teseda, sees promise in that approach but estimates that even the best BIST implementations will require "topping-off" test vectors to raise test coverage from BIST's 95%, for example, to a design's 98% or 99% target coverage. And according to Andrew Levy, Teseda's director of marketing, scan will more quickly adapt to ever-shrinking processes than will pure BIST.

Morris sees ATE systems fitting into three tiers:

• Big-iron testers, such as the Teradyne Catalyst, which can provide complete at-speed functional tests,
• Middle-iron testers, such as Agilent Technologies' 93000, Schlumberger's DeFT, and Teradyne's Integra Flex, which combine structural and functional test capabilities, and
• Low-cost DFT-only testers having no functional-test capabilities at all.

Teseda, a startup not currently offering a product, plans an entry in this last tier by year's end. Morris says such an all-digital tester can be cost effective for wafer probe of even mixed-signal devices. Scan test at wafer probe, he says, can drastically reduce the time that a mixed-signal packaged DUT would occupy on a big-iron functional tester such as a Catalyst.

If you can cut Catalyst test times from 10 s to 2 s per DUT using a low-cost tester, then you've accomplished something, says Morris. Teradyne's Driggs concurs, although he not surprisingly recommends the Integra Flex for the wafer-probe role.

You can expect to see ATE and DFT vendors cooperate as they strive to meet the needs of semiconductor designers and manufacturers. Structural test is well established, especially in the digital world, and you can expect significant progress in the mixed-signal world as well.

Keep in mind, though, that structural-test techniques will undergo continual evolution. Schlumberger's Garcia points out that there's nothing more unstructured than structural test. Product designs zoom a generation ahead, and structural tests that could completely verify yesterday's products will always need an assist from full at-speed functional test techniques.