What PAM5 means to you

From its early applications in the 1960s for T1 communications services, multilevel signaling has played an important role in increasing the data rates that existing wire infrastructures could support, providing high-speed symbol-transfer rates at relatively low observed line rates. Today, a version called 5-level (quinary) pulse amplitude modulation (PAM5) enables Gigabit Ethernet (GbE) to achieve sustained data rates of 1 Gbit/s over four Category-5 (CAT-5) parallel differential signal lines, each operating at only 125 MHz.

To ensure that the ICs that implement PAM5 are high quality—for example, able to support GbE-specified bit error rates (BER) of less than or equal to 10^-10—you'll need a flexible test architecture that can perform critical jitter and envelope tests and that can address the complex functional-test requirements of multilevel-signaling ICs (see "Functional test for GbE devices").

Figure 1 Quinary pulse-amplitude modulation (PAM5) uses four signal levels to represent two bits; the fifth level provides for forward error correction.

In PAM5 encoding, each transmitted symbol represents one of five levels: –2, –1, 0, +1, +2 (Figure 1). Four levels represent two bits; the fifth level supports forward error correction (FEC) in the form of four-dimensional eight-state Trellis coding. Using hybrids and echo cancelers, the 1000Base-T physical layer achieves full-duplex transmission, allowing simultaneous symbol transmission and reception on one wire pair. Consequently, each wire pair attains 250-Mbits/s throughput using 125-Mbaud baseband signaling—achieving 1-Gbit/s rates at a spectral power density similar to that of 100Base-TX. As a result, companies needn't replace wires when upgrading existing 100Base-TX networks; they can simply upgrade their network interface cards, leaving installed wiring in place.

GbE test strategy

Although multilevel signaling methods offer substantial benefits, they can increase test costs and delay volume delivery of GbE devices. When testing the receiver side of these devices, engineers must verify proper frequency and voltage parameters on the receiver side and verify the ability of a device to successfully translate the scrambling and bit redefinitions that produce a recognizable bit pattern. On the transmitter side, production tests need to confirm that a pseudo-random signal results in proper voltage levels and bit patterns on all four output ports.

Tests of multilevel signaling require fine-resolution measurement of analog amplitude, voltage, and distortion. In addition, test equipment must convert complex multilevel signals to their corresponding high-speed digital data streams to verify that the device functions properly.

IEEE 802.3ab specifies four test modes for verifying GbE devices (see "GbE baseline tests," below); each of the modes specifies a waveform that must appear on all four of the wire-pair interfaces simultaneously. You can use a subset of the tests to verify signal integrity, timing, and functionality during production. For these tests, you'll need a test setup that includes arbitrary waveform generators (AWGs), high-speed processors, and instrumentation with multiple independent differential channels.

You can verify signal integrity in a GbE device using just three tests from test mode 1 in IEEE 802.3ab:

• transmitter maximum output droop, which measures signals at predefined points to verify the device's ability to exceed certain minimal voltage droop levels;
• transmitter differential output template test, which verifies that transmitter output equalization meets specifications and shows whether a normalized waveform fits within a standard template; and
• transmitter peak differential output voltage and level accuracy, which verifies output accuracy.

In this third test, an analog capture processor (ACP) uses differential inputs and DSP analysis techniques to measure levels. The standard requires that the value at four different points be determined from a filtered waveform using the high-pass filter described in the standard.

Figure 2 (a) An analog capture processor (with four differential inputs) and an arbitrary waveform generator simultaneously measure output voltage on four channels. (b) The ACP can also be configured to measure jitter on all four twisted-pair outputs from a DUT.

The test setup in Figure 2a measures output voltage-level accuracy simultaneously for all four twisted-pair outputs from the DUT. The tester should have an ACP with four differential inputs as well as a precision clock source for the 125-MHz input in order to locate the DUT transmit edges. This test should measure transmitter performance in the presence of a remotely driven signal, but providing a remotely driven signal during production test isn't practical.

Consequently, an AWG can serve as an alternate representative disturbance, providing a 2.8-V p-p sine wave at a 31.25-MHz frequency with harmonics 40 dB below the fundamental, as 802.3ab specifies. The resulting mode 1 waveform from the DUT will droop and distort (Figure 3). The degree of droop and distortion will determine whether a device passes or fails this test.

Figure 3 The degree of droop and distortion in a DUT's test mode 1 waveform determines whether the device passes or fails.

To create disturbances on multilevel signals, your test system must be able to transmit at least 2.5 Gsamples/s. With 8-bit samples used for GbE devices, waveform files can become large, necessitating memory depths on the order of 8 Mbytes. And because simultaneous signal generation or measurement across all four wire pairs is a repeating theme in 1000Base-T testing, you'll find it useful to have an AWG with four buffered outputs.

If you used an AWG that had only one output and had to be switched between wire pairs, the test time would rise accordingly, and you wouldn't be able to uncover potential interactions such as crosstalk noise between wire pairs. You could use a separate AWG for each of the four wire pairs, but that would increase instrument cost.

You can check a device's timing performance using three timing measurements derived from test modes 2 and 3 in IEEE 802.3ab:

• transmitter clock frequency, which verifies that the quinary symbol transmission rate on each pair is 125 MHz, 60.01%;
• receiver frequency tolerance, which verifies that the receiver can properly receive incoming data with a 5-level symbol rate of 125 MHz, 60.01%; and
• transmitter timing jitter, which verifies minimum jitter characteristics.

The first two tests require measurement resolution of at least 12.5 kHz, which is well within the capability of most production test systems. The transmitter timing jitter test, however, can present problems with measurement coherency, where the use of separate clocks in the test setup can degrade the resolution of the timing measurement.

The test setup in Figure 2b shows the configuration needed to measure jitter for all four twisted-pair outputs from the DUT. Once again, the tester should provide an ACP with four differential inputs and provide a precision clock source for the 125-MHz input in order to ensure that the tester itself does not contribute a significant amount of jitter to the measurement.

The 802.3ab standard states that the jitter can be determined by measuring the zero crossings for at least 105 clock edges of a filtered data stream using the specified high-pass filter. In addition, the standard specifies that the peak-to-peak jitter of the filtered output must be less than 300 ps, so the jitter resolution of the measurement— and, hence, the resolution of the tester—needs to be better than 300 ps.

Some commercial ATE systems have a resolution of 62.5 ps, which works well in this application. If the maximum samples are taken over this time period to get the finest jitter resolution possible, there would be (8 ns x 105)/62.5 ps, or 12.8 Msamples taken per each of the four channels. This allows for 128 samples per cycle with which to determine the location of each zero crossing of each cycle.

Digital signal processing can find all of the crossing points within these 105 data samples. The tester should compare these crossing points with the TX_TCLK crossing points to arrive at the maximum peak-to-peak jitter. A key factor in this test is that the clock source used by the DUT must be coherent with the tester. The ACP must also trigger from the DUT clock, which must be coherent with the master clock used by the ACP and the AWG. Data not collected using this coherent clocking and triggering approach would be difficult, if not impossible, to sort out.