Memory BIST for at-speed test
-- Test & Measurement World, 10/1/2004
Increased integration with nanometer processes is resulting in some devices
that are using hundreds of small memory blocks distributed throughout the
design. Memory BIST can be used to apply standard memory test algorithms to
detect the majority of defects within memory arrays.
Adding memory BIST controllers and routing for tens of memories is
reasonable. Adding the logic and routing for several hundred memories or
register files will produce a notable impact on the device. With the increase in
area also comes an increase in yield loss. Furthermore, designers do not want to
deal with the routing and performance impact due to BIST access and muxing for
hundreds of memories. On the other hand, if the small memories are not tested,
test quality will be reduced and the DPM rate will increase.
Testing memory arrays using standard memory BIST algorithms
begins to fall short of quality requirements when applied to nanometer designs.
At smaller process technologies, more timing defects occur within the memory
that need to be tested. Even though many memory BIST controllers use PLLs to
clock the BIST operations, these operations usually take several cycles to
complete. For example, a write operation may use one cycle to set up a new
address and a second cycle to pulse the write clock.
Full-speed memory BIST is a technique used to perform at-speed testing but with back-to-back write and read operations. Memory operations are pipelined such that as a write clock pulse is occurring, the address for the next operation is provided in the same cycle. Not only will the BIST tests complete faster, but the testing will be more accurate in detecting timing defects (Ref. A).
Memory BIST and full-speed memory BIST are good solutions for the large memory arrays. But when devices have hundreds of smaller memories, it is not an effective solution to implement, especially for performance-critical memories. Small memory devices also need to have some type of memory test algorithm applied to them to avoid holes in the test quality. Adding memory BIST controllers is not possible for many of these small memories. It is common to have many register files with only a small address space. Adding memory BIST could require much more area than the memory itself.
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| Macro testing converts each functional pattern into individual scan-chain loads and captures. |
A technique called macro testing was developed to test these small memories
without adding any additional logic or routing. Macro testing takes advantage of
ATPG tool capabilities to algorithmically determine how to supply specific
internal values through scan cell loading. In other words, macro testing will
take a pattern set that corresponds to a memory instance (or other type of
instance) and convert it to a scan pattern. No logic is needed to supply the
pattern values to the memory.
ATPG processes will load
scan cells such that the appropriate values are available at the memory inputs.
ATPG will also ensure that the expected responses are propagated to scan cells
for capture and verification. Macro testing has been effectively used to test
over 400 different memories in parallel.
In addition, macro testing can be used to apply sequences of at-speed test patterns. The ATPG processing can determine how to load the scan cells several sequential levels back. Once the clock is pulsed, the newly captured scan cell values will correspond to the next operation. This allows write-read-capture at-speed tests using this technique.
A read operation cannot be followed by a write operation in an at-speed macro test pattern because it wouldn’t allow the read values to be verified. The named capture procedure use of PLLs for at-speed testing can also be used for at-speed application of macro test clocks.
Reference
A. Powell, T., et al., “BIST for
Deep Submicron ASIC Memories with High Performance Application”, International
Test Conference 2003.
