ITC Speakers Address Yield Enhancement
Rick Nelson, Chief Editor -- Test & Measurement World, 10/27/2004 5:44:00 AM
Charlotte, NC. Bernd Koenemann, chief scientist at Mentor Graphics, on Tuesday kicked off this year's ITC, held here this week, with a keynote address titled “Test in the Era of ‘What you see is not what you get.’” His presentation was followed by an invited address from Robert Madge, director of product engineering at LSI Logic, who described new test paradigms for test and manufacturability. Both speakers described yield enhancement as a key factor that test can address.
Koenemann began his talk describing process-related defects caused by “dirt” (for example, particle contamination) or equipment problems. Such defects, he said, can cause catastrophic or parametric failures and may be visible to in-line inspection equipment, and their presence can be characterized by on-chip test structures. In contrast, design-related defects can also cause catastrophic or parametric failures, but they can be invisible and may not affect test structures.
He cited two camps of participants and their views of test: the “propeller heads” of the EDA community think in terms of netlists and abstract faults serving as input to an automatic test-pattern generator, resulting in a specific test-coverage figure, while the “screwdriver people” think in terms of silicon, defects, and yield.
Problems for both camps, he contended, stem from sub-wavelength lithography, in which printed-image quality suffers as feature sizes reach a resolution limit. With sub-wavelength lithography, optical proximity effects (OPE) can cause catastrophic or parametric defects (the latter because of potential variations in resistances and cross capacitances). Such problems can be ameliorated by optical process correction (OPC), which overemphasizes portions of, and may add scattering bars to, an original lithographic pattern to assure the correct pattern is printed on a wafer.
Other problems come in to play as well, he said. For example, defocus effects resulting from a wafer’s lack of true planarity can cause deviations, such as gate-length variations, that can result in localized concentrations of defects—“bad neighborhoods,” as he put it. He also cited signal-integrity issues with respect to noise, crosstalk, and IR drop as well as spatial and temperature-related intrachip variations.
He concluded that currently, feature-dependent issues are becoming predominant in limiting yield, stating that it’s very difficult for EDA tools alone to provide design closure. What’s needed, he said, are not the separate approaches of the “propeller head” and “screwdriver” camps. Similarly, he’s not ready to jump to new fault models, although he won’t rule them out for the future. What he proposed is instead an integrated approach that takes into account parametric constraints, netlists, faults, and wafers. The best approach, he said, would identify good parts to ship while screening out the failures. But further, it would provide for data mining on failed devices to provide the feedback necessary to assist with yield-improvement learning.
LSI Logic’s Madge, in his address, concurred with many of Koenemann’s points, citing, for example, sub-wavelength lithography and the parametric deformations that potentially can cause problems in modern semiconductor manufacturing. In addition, he added, disaggregation of the semiconductor industry. He said that parametric, systemic, and random yield losses are all a function of design, fabrication, and test. Like Koenemann, he said that a feedback mechanism that provides for learning based on test results is beneficial. As a first step toward what he called “raw test-data visualization,” which helps to describe defect behavior.
In his experience, Madge said, systematic defects at the edges of process windows are becoming predominant, displacing the importance of random defects, which have been the traditional targets of ITC presentations. He cited as an example a situation in which every fourth wafer exhibits failures related to a particular scan chain. He said it’s helpful to have a raw test data to serve as feedback to help contain such excursions.
Madge commented on traditional design rules, which a design either did or did not meet. Such rules, he said, don't indicate feature-related yield variations—designers don't have sufficient amounts of statistically valid data to make meaningful statistical decisions.
Alluding to this year's ITC theme, “Testing from fab to field,” Madge said that what's required is testing from design to field, with data feedback to the design phase as well as to all the intermediate steps—wafer fabrication, board assembly, system assembly, and so on—as a product progresses toward its end customer.
Statistical and adaptive testing, he said, with adaptive outlier screening, are initial steps toward more effective test strategies. He concurred with Koenemann that data analysis must play a key role. According to Madge, data analysis can fine-tune the amount of structural test, functional test, and burn-in required for various devices under test based on previous results. To that end, he concluded, ATE must do a better job of collecting and saving parametric test data.
