Boundary scan test: encapsulation or integration?
A paper accompanying our March 2006 Sieca Test Digest article, "Integrating boundary scan into ATE channel cards."
David Sigillo, Seica -- Test & Measurement World, 3/1/2006 1:00:00 AM
In the mid 80s, a group of industry pioneers, the Joint Test Action Group (JTAG), started meetings in a hotel near the Amsterdam airport, invited by Philips, to put down the first stone of one of the most successful constructions of the test community: boundary scan. Today codified as the IEEE 1149 standard, boundary scan is a universally accepted technology to embed testability into integrated circuits, in order to ease test at the board, box, and system level.
Several working teams have ongoing activities in different application domains. The most successful today is the 1149.1 standard, the first to be adopted (in 1990). It specifies a testability bus to resolve assembly-test problems for loaded boards. Using a shift register associated with all cells of the I/O pins of an IC, plus a 16-state engine (TAP, for Test Access Port) added to the component itself, a user can gain full external and internal control of the I/O functions of the device. Once the IC is mounted into a board, by accessing only four signals (TDI, for Test Data Input; TDO, for Test Data Output; TCK, for Test Clock; and TMS, for Test Mode Select), an engineer can automatically generate sequences of serial tests to verify correct connectivity to the board. When more than one component with boundary scan is present on the board, you can chain TDI and TDO lines of JTAG devices to obtain the same results of conventional in-circuit test techniques without requiring intrusive nail access (Figure 1). The dream of maximum fault coverage for minimum test cost is finally at hand.
Extending applications
After an initial period of reluctance to adopt the bus (because of added cost, inexperience, and design-test miscommunication), today the field of application of boundary scan is enlarging. Initially all interest was around in-circuit test, as the technique did not require writing complex test models for ASICs with unknown internal logic. The decreasing internal access available on boards now has favored boundary scan for interconnection test as well as for verification of internal board clusters (employing non-JTAG technology). Today, all aspects concerning the customization of boards are involved, including the programming EPLD, flash, and FPGA devices. Furthermore, design engineers are using the technique in the early prototype stages to gain access to the internal buses of a board and to perform microprocessor emulation under their control.
Test strategies and scenarios
Because of the simplicity and elegance of the approach, the first temptation would be to throw away all existing bulky and expensive automatic test equipment (ATE) and fixtures and replace them with bench-top dedicated boundary-scan testers. A PC, a control card, and four wires would replace all existing test assets. Indeed, the simplicity and low cost of this approach has favored acceptance of boundary scan by the engineering community, and bench-top boundary-scan systems are more and more frequently used to assure a quick test of structural integrity of the board prototype, to debug hardware, or to download and verify embedded software.
 |
| Figure 1. Four lines (Test Data In, Test Data Out, Test Clock, and Test Mode Select) provide for thorough tests of JTAG-compliant devices. |
This lab-oriented approach becomes, however, insufficient to assure high-quality production and maintenance test later on in the life of the board. In fact, despite the growing acceptance of the standard, JTAG components rarely cover the totality of the integrated components on a board. Therefore, non-JTAG components also need to be tested, and more than four wires are then required. Discrete components are also populating the board, and conventional test techniques are required to check for their integrity and to diagnose faults. Also, testing for structural faults with JTAG techniques requires that a tester power-up a board, although an initial, conventional power-off in-circuit test for shorts would be safer. Finally, despite increasing performances of the JTAG controllers, which can offer test speeds of 30 MHz and more, JTAG remains a serial test technique. On-board-programming via JTAG ports might become too lengthy a process to be acceptable in production test, which can benefit from the parallel architecture of an in-circuit tester.
To fully cover manufacturing and maintenance test issues, three scenarios are currently deployed:
- the extended bench-top test strategy,
- the dual test strategy, and
- the ATE encapsulation test strategy.
Extended bench-top test strategy
If we decide to concentrate all tests around the bench-top JTAG system, to increase fault coverage we need to add I/O channels, instrumentation, and test-generation tools. In other words, we need to build the missing ATE characteristics around the JTAG tester core. This strategy is of course valuable if the JTAG content on the board is predominant, production volumes are small, and cost considerations make it the best compromise. Because of the limitations of the original platform, of the lack of base test techniques or development tools, and ultimately of the fragility of the overall infrastructure, this remains a niche strategy, rarely growing outside of prototype or pre-production test environments.
Dual test strategy
A dual test strategy balances test across a conventional in-circuit tester (often a flying-probe system) followed by a JTAG bench-top station. Each system addresses what it can do best, with a “divide and conquer” approach. To avoid redundancies and duplications, software tools exist to determine how the test-development effort should be split and to calculate the final, combined fault coverage.
Test strategies involving a flying prober followed by a JTAG system are increasingly being adopted, taking advantage of the ease of test generation, a fixtureless approach, and the complementarities of the two techniques. A major drawback, however, is the operating cost due to the usage of two test stages. Throughput might also become a problem, as neither system excels at high-speed test.
ATE encapsulation test strategy
Concentrating non-JTAG and JTAG test on a single, conventional ATE system is the natural third strategy. Initially, ATE manufacturers tried to do so by using conventional architectures and by developing their program-generation tools to cover JTAG applications. This approach has quickly faded out for two reasons: the inadequacy of the hardware and the need to re-develop test programs instead of incorporating those already used by engineers at the prototype stage.
A more successful step has consisted of plugging the external JTAG controller into the ATE, giving it access to the fixture, and dealing with it as ATE deals with other intelligent instruments. The ATE will carry out all conventional tests through its test-generation tools and parallel channels, and it will rely on the test-generation tools and test execution of the encapsulated JTAG controller for boundary-scan tests.
Though ATE vendors would claim seamless integration, we are indeed dealing with a hybrid encapsulation of the JTAG tools, with many advantages but also some limitations. The main advantage of this approach is the ability to re-use the same tests, hardware, and software that was developed in engineering, encapsulating those resources on conventional ATE that would take care of all the other test requirements.
 |
|
Figure 2. Integration of a JTAG controller into ATE channel cards enables the ATE channels to be controlled both by the base ATE controller or by the JTAG controller, depending on the specific test steps being executed. |
The main limitation is in the encapsulation approach itself. As applications for JTAG tests extend, they will tend to require parallel access to non-JTAG I/O. Indeed, JTAG test benches use additional I/O channels to control test points, to do cluster test, to check continuity between JTAG and non-JTAG components, and so on. But once encapsulated in the ATE, the JTAG controller does not have any control over the ATE channels. Repeatedly swapping from the ATE to the JTAG controller and back is unpractical. Adding the JTAG I/O channels to the ATE might make sense if the target ATE is a flying prober; in other cases it will create complications to fixture wiring, at minimum.
A step beyond: full ATE integration
 |
|
Figure 3. The Valid line of functional ATE (shown) incorporates JTAG access to top-line channel cards, providing for full ATE integration with any external JTAG resource. |
The debate between JTAG or non-JTAG test supporters will finally end, on a seamless, effective ATE integration. T&MW
Dave Sigillo, based in Methuen, MA, has served as US general manager for Seica (headquartered in Strambino, Italy) for three years. He previously held several positions in product management for functional test at GenRad and Teradyne.
