Novas debuts visibility-enhancement tools

-- Test & Measurement World, 3/6/2006 7:21:00 AM

Novas Software, a vendor of debug systems for complex chip designs, has announced its new family of Siloti Visibility Enhancement (VE) products to address the problem of decreasing visibility into the functional operation of complex ICs during late-stage verification and system validation.

The Siloti products aim to overcome the problems of limited signal observability in near- and post-silicon applications with patent-pending visibility-enhancement technology that, the company says, improves simulation, emulation, first-silicon prototyping, and silicon-debug methodologies. The company further says that initial customer results demonstrate that Siloti technology cuts debug cycles by as much as 4X when employed with hardware emulation and that it improves design visibility by 5X when deployed with design for debug (DFD) methodologies. The underlying Siloti visibility-enhancement technology analyzes limited signal data; automatically derives missing information; and correlates complex low-level representations with RTL descriptions.

Novas is delivering its visibility enhancement capabilities through a series of application-specific products, starting with its Siloti SilVE and SimVE offerings. These first two Siloti products work with third-party simulation, emulation and FPGA-based prototyping tools, as well as with emerging DFD tools and test environments. The Siloti tools are also tightly integrated with Novas’ Verdi automated debug system to bring RTL debug to visibility-challenged environments. 

“The gap between first silicon and volume production is widening and verification is straining due in large part to the lack of visibility into the behavior of the design. There is simply too much data and limited observability. Existing methodologies are inefficient because they require multiple iterations due to the extreme expense of visibility,” said Scott Sandler, president and CEO of Novas. “We are expanding our focus beyond debug to tackle these issues with a new class of visibility enhancement technologies and products. The net result is reduced cost of verification and shorter time to shipping fully validated ICs.”

In today’s IC design flow, the difficulty of observing signal data increases and visibility into the operation of the design decreases as verification progresses. In early simulation runs, full visibility is achieved by dumping as many signals as needed. But in full-chip regression simulation, the number of signals is so large that dumping everything becomes prohibitively expensive, and users must be selective. This problem becomes even more severe in emulation, prototype, and actual-chip situations because access to signal data is only through logic structures that must be inserted into the hardware.

“The development of our complex high-performance, low-power PWRficient processor requires a verification strategy that is extremely rigorous and relies heavily on emulation and DFD methodologies for system validation,” said Tse-Yu Yeh, director of architecture and verification at P.A. Semi. “With Novas’ Siloti visibility enhancement and Verdi debug platforms, we cut our debug cycles by 4X during emulation while actually debugging more of the design. The essential signal analysis capabilities also enabled us to maximize overall visibility using DFD logic without exceeding our area constraints.”

The Siloti SilVE product works with emulators, prototypes, and DFD-enabled chips to optimize observability of signals. It first compiles the HDL design and performs formal analysis to determine which signals are essential. This information can guide insertion of access points or probes into the device so that the required signal data can be obtained during emulation or operation of the prototype. The Siloti abstraction correlation and data expansion engines then work together to automatically map the low-level structures of the actual chip up to the RTL level and expand the dumped data to fill in the gaps for full visibility. Novas is awaiting patent approval on its process for providing RTL-level visibility for chip-level data.

The Siloti SimVE product works with standard HDL simulators to make regression simulation more efficient. With current methodologies, engineers often run multiple regression simulations, first without dumping any signal data, and then again when a problem is discovered dumping only data they estimate is necessary for debug. If they guess wrong, another iteration is required. By deploying an optimized methodology that limits dumping to a small but critical subset of signals, SimVE users can achieve full-chip functional debug with a single regression run and minimal impact on simulator performance.

Both the Siloti SilVE and SimVE products are tightly integrated with the Novas Verdi debug system, such that the Siloti data expansion engine is automatically invoked when users request visualization or tracing of data that was not dumped.

Base price: $65,000 for an annual license.

Novas Software, www.novas.com/Solutions/Siloti/
P.A. Semi, www.pasemi.com