Test's role on the path to zero-defect devices

The automotive industry will increasingly be required to focus on zero-defect methodologies for digital integrated circuits.

Mick Tegethoff and Vivek Chickermane, Cadence Design Systems -- Test & Measurement World, 6/1/2006

The effectiveness of semiconductor manufacturing test directly impacts the quality and reliability of shipped silicon and the economical efficiency of overall test costs within the supply chain. Typically, suppliers and customers negotiate agreements on acceptable Defective Parts per Million (DPM) levels representing an optimum tradeoff between test coverage and device cost.

Automotive zero-defect methodology

In many applications requiring zero defects, the focus over the years has been to concentrate on testing analog circuits to address overall reliability concerns. Traditionally, semiconductor suppliers and their customers did not devote expensive resources to the test of digital components because digital content was relatively small, and digital logic is predictable in terms of its defect behavior. In the case of analog circuitry and measurements, the industry has developed methods to drive toward zero defects deploying improvements in test coverage and reliability screening.

One example of this effort is a methodology being advocated by the Automotive Electronics Council (www.aecouncil.com) called Parts Average Testing (PAT) (Ref. 1). PAT is a statistically based method for removing parts with abnormal characteristics (outliers) from the automotive semiconductor supply chain.

The automotive test ecosystem

Figure 1 depicts the automotive module manufacturing test ecosystem extending from semiconductor supplier to automobile assembly and finally to the end customer. In the ecosystem, once the semiconductor device passes package test it is shipped to a module supplier that incorporates the device within a module composed of one or more printed circuit boards (PCB) and multiple semiconductors. Testing at the module level typically consists of an application of a combination of PCB interconnect tests and a functional test of the module. Once the module passes all tests, it is shipped to the automobile manufacturer who integrates the module with all other electronic components in the product.

To illustrate the magnitude of the economic challenge in the automobile supply chain, consider the case of a defective semiconductor costing $15 that is used in a controller unit costing $150 and assembled into an automobile worth $35,000. The result of a defective device escaping the test process at the semiconductor supplier has a very significant impact on the profitability of the entire supply chain. This is without even considering the reliability aspects of the situation (Ref. 2).

From the economic impact alone, zero defect devices are justified for the automobile industry. As the digital content of automotive semiconductors grows at an exploding rate, a zero-defect methodology for the digital circuitry becomes a requirement for semiconductor suppliers. Another complication is the increasing use of embedded software causing unintended hardware/software interactions. As in the case with computers and other consumer products, automobile electronics will continue to deploy increasingly complex applications, moving from simplistic ROM-based microcode to sophisticated operating-system-based applications. In this environment, hardware/software interactions make detecting all manufacturing defects early in the supply chain more difficult and more expensive.

Figure 2 depicts the semiconductor manufacturing test ecosystem extending from design and verification through to wafer sort, final manufacturing test, and on to diagnostics. There are two major steps in semiconductor test: wafer sort and package test. The current practice in the industry is to use primarily structural methods, such as scan test, to detect manufacturing defects in the digital circuitry and to use traditional instrument-based measurements for the device's analog aspects. There has been limited progress in the industry in both the automation of analog tests and the formal integration of analog and digital tests on a single device.

Nanometer digital test

Digital test has made significant progress in both design for test (DFT) and automatic test pattern generation (ATPG) technologies. EDA suppliers have offerings that will insert all of the required digital DFT features into the design during the logic synthesis flow. Not only is the technology available, but there is significant economic motivation to deploy a highly automated test technology to nanometer digital designs. There has been limited focus on the aspects of "zero defects" for digital tests, however, because the dynamics of the traditional electronics consumer markets have not made it a top requirement.

Today, mainstream digital designs are migrating from 130- to 90- and 65-nm technology nodes. At these advanced nodes, defect behavior of digital circuitry is far less predictable with traditional fault models. A nanometer test strategy has been outlined (Ref 3); it includes the traditional structural-test techniques, as well as specialized fault modeling and test procedures to detect the subtle timing defects appearing in nanometer designs.

Low DPM designs today require a full-chip test infrastructure; the ability to perform stuck-at, at-speed, and faster-than-at-speed tests (Ref. 4); and specific tests targeting defect-based fault models--all within an architecture supporting test cost containment by using on-chip pattern compression. In addition, nanometer process improvement requires volume and precision diagnostics to identify systematic yield limiters and to locate the root cause of failures.

Parametric and analog tests

In addition to structural testing, digital designs also employ parametric tests that measure parameters such as leakage current on drivers and receivers. Another method in wide use is quiescent current testing, which measures the static current draw on the power supplies of the chip (I_DDQ). I_DDQ tests are performed by creating a small set of vectors that put the device in a powered but non-switching state, after which the drawn current of the power supply to the device is measured.

In a defect-free device, the measurement will be relatively small because the only current being drawn is leakage current on the CMOS FETs. In the presence of a defect, however, the current level due to leakage will be higher and the test will fail. Also, I_DDQ tests for larger devices in nanometer technologies are less effective because the static current drawn is higher, making it difficult to differentiate the presence of a small defect.

Analog test remains the domain of expert designers, and in many cases it is a competitive differentiator for semiconductor companies. Analog designs are typically small, and tests can be effectively generated using semiautomated methods. Analog designs offer limited pay back for highly automated test methods compared to the case of large digital designs.

In general terms, analog blocks are tested by measurements of the block functions as predicted by their "data sheet" min and max specifications. These tests are generated semi-manually and are made of a limited number of test steps, since they take a relatively long time to execute on a tester. Analog tests by their nature are suitable to the PAT type of methodology since one is performing analog measurements over a wide sample size.

The test process

Referring to the flow depicted in Figure 2, the digital tests are composed of DFT insertion to enable high test coverage when the ATPG generates the test patterns. Once in manufacturing, the digital tests are combined with device parametric tests, I_DDQ tests, and tests for the analog blocks into a test program executed on the automated test equipment (ATE).

There are four possible outcomes of a test step:

• a good device (the test passes a device that is defect-free);
• a test escape (the test passes a device that has one or more defects);
• a bad device (the test fails a device that has one or more defects); or
• a false fail (the test fails a device that is defect-free).

Devices that pass the test are shipped to the next level of integration, and devices that fail the test are scrapped. Diagnostics can be used to understand why devices failed in an effort to correct the design or the manufacturing processes and improve device yield. Digital test failures can utilize advanced diagnostic products that can analyze large volume of failures to identify trends and then identify the root cause of the top yield detractors.

Reducing test escapes

Zero-defect testing has the objective of eliminating test escapes--that is, to catch all defect devices prior to them "escaping" to the next level of integration. It also is important not to generate false failures, as they will negatively impact yield and profit.

In order to illustrate efforts being carried out in the industry to reduce test escapes in digital designs, the results of a case study using a statistical defect quality model that relates the probability of test escapes measure in parts per million (PPM) as a function of the timing of the ATPG generated transition test for nodes in a digital circuit have been described (Ref. 5).

Figure 3 shows the results of this case study using three different designs. The model reflects fabrication process quality, design delay margin, and test timing accuracy. It provides a metric that can predict the level of test escapes that cause delay failure, including marginal delay.

We can therefore use the model to compare ATPG-generated test vectors in terms of the resulting test escape level. To evaluate the test effectiveness as a function of the timing of each test, the results of tests generated at different test speeds were compared in this case study. It reports results for the following types of transition tests:

1. Fixed-time (no circuit timing information). The test clock was set at the system clock, but requires manual removal of tests that failed timing. This typically results in lower coverage.
2. At-speed (with circuit timing information in the industry standard SDF format). This typically achieves higher coverage than fixed time because the ATPG will automatically choose paths that meet timing for tests.
3. Faster than at-speed (With SDF as above). This method uses three types of tests:
   • Slower than at-speed tests for multi-cycle paths. The test launch-capture cycle is longer than the nominal functional clock cycle time.
   • At-speed tests for nominal paths, which is the same as (2) above.
   • Faster than at-speed for small delay defects in short paths.

The above tests were generated using a commercial tool (Ref. 6). Our objective with this experiment was to provide a comparison as a relative measure. The model results for "fixed time" is set as the baseline at 100%, and the graph shows the relative percentage reduction in test escapes for the other types of tests. Chip 1 achieved a 40% relative reduction from fixed time to Faster than At-Speed.

This examples show that there is much that can be done in digital testing to reduce test escapes and make progress on the path to zero defects. It is clear that for all designs the test-escape number for the patterns generated at a faster speed was reduced. That is, the pattern quality of these patterns is better than those of the patterns generated at a slower speed, and, as a result, the number of test escapes is significantly reduced.

Bringing zero defects to digital tests

If one were to combine the advances in digital test technologies with the practices of automotive testing, there is significant benefit to the semiconductor test process of automotive devices. The first opportunity is to apply PAT testing methods to the parametric aspects of digital testing.

One of the challenges of I_DDQ testing is to determine the threshold of passing versus failing devices. Some technologists propose determining ranges of "acceptable" I_DDQ levels. I_DDQ and parametric digital tests are prime candidates for methodologies such as PAT. Figure 4 shows the primary statistical methodology for PAT tests.

Figure 4. Shown here is a graphical representation of part average test limits and outliers.

PAT limits represent the application of statistical techniques for the removal of abnormal parts during part-level testing. A device specification defines the requirements needed for the part to work properly within its application. Every part is built with a particular design and statistical process control (SPC) controlled process that, if processed correctly, will yield a certain consistent set of characteristic test results.

PAT uses statistical techniques to establish the limits on these test results. These test limits are set up to remove outliers (parts whose parameters are statistically different from the typical part) and should have minimal yield impact on correctly processed parts from an SPC controlled process. The intent of PAT is to increase the quality and reliability of parts by removing abnormal parts as early in the part manufacturing sequence as possible. This should minimize costs related to customer support and failure analysis, and it should provide early feedback to prevent the occurrence of quality accidents. PAT can be applied to parametric tests as well as I_DDQ tests, and the same methodology can be taken even further.

The next opportunity is to consider applying the PAT methodology to structural tests. Some advanced ATPG products have the capability of generating tests using the digital circuit timing information. With this capability, one could additionally determine pass/fail criteria based on a transition fault failure characterized by the appropriate range of acceptable devices. Special tests could be created that would fail devices that fall outside that range following the PAT methodology.

This is the next frontier in the advent of statistical timing for digital devices. It has been shown that for leading edge technologies, the statistical aspects of timing within the die and wafer as opposed to solely one min/max value for each timing path must be considered. In particular, there is significant effort today on timing analyzers that employ statistical timing methods as opposed to discreet timing. There will be an opportunity in the future to combine the statistical nature of timing analysis with screening for zero defects. The semiconductor industry will not be short of challenges as it strives to improve the overall quality of the semiconductor supply chain.

This article has described the aspects of zero defects testing for automotive devices. In the future, the industry will be required to focus on zero defect methodologies for the digital components of automotive semiconductors. It has highlighted different approaches for digital and analog testing, and described automotive zero defect methodologies such as PAT. Finally, it outlined opportunities to apply PAT testing to digital tests.

REFERENCES

1. AEC - Q001 Rev-C July 18, 2003, "Guidelines for part average testing," Automotive Electronics Council, www.aecouncil.com

2. "Chrysler electronics exec pushes 'zero defects,'" Power Electronics Technology, February 3, 2005, powerelectronics.com/autoelectronics/exec_pushes_tolerance/index.html.

3. Keller, B., et al, "An Economic Analysis and ROI Model for Nanometer Test," Proceedings of the 2004 IEEE International Test Conference, www.itctestweek.org.

4. Amodeo, Martin, and Bruce Cory, "Beyond at-speed," Test & Measurement World, November 2005, www.reed-electronics.com/tmworld/article/CA6277905.

 5. Y Sato, et al, "Evaluation of the Statistical Delay Quality Model," Proceedings of the Asia and South Pacific Design Automation Conference 2005, www.aspdac.com.

 6. "Encounter Test," Cadence Design Systems, www.cadence.com/products/digital_ic/encountertest/index.aspx.

Mick Tegethoff is group director for Encounter Test product marketing at Cadence Design Systems. He has over 20 years of experience in design, manufacturing, and test of semiconductors and electronic products. Prior to Cadence, he held various technical and marketing positions in the electronics industry, including 10 years at Hewlett Packard. Tegethoff holds a PhD in Electrical Engineering with a focus on test economic modeling.

Vivek Chickermane is senior architect for Encounter Test at Cadence Design Systems. Prior to joining Cadence, he served in IBM's Microelectronics Division, where he was responsible for design-for-test synthesis. He has a PhD in Electrical Engineering from the University of Illinois at Urbana-Champaign.