An IC DFM vendor sampler
Rick Nelson, Chief Editor -- Test & Measurement World, 6/6/2006 6:02:00 AM
Point-tool vendors with a claim to the "design for manufacturing" (DFM) label might offer products embodying optical proximity correction (OPC) and resolution enhancement technology (RET), or they might provide design-rule-checking (DRC) tools, timing and power optimization packages, lithography simulators, or yield measurement and analysis tools. Below is a sampling of integrated-circuit DFM point-tool vendors, products, and technologies. Updated August 24, 2006.
• Read related commentary here.• Find links to recent DFM coverage in Reed Electronics Group publications here.
| Company | Product and technology |
| Anchor Semiconductor http://www.anchorsemi.com/ |
NanoScope-PRV OPC/RET inspection tool; NanoScope-DFP manufacturing-aware design verification tool, which is used at pre-tapeout and is complementary to DRC to ensure lithographic-friendly layout; NanoScope-YAM full-chip design-based hot-spot analysis tool. |
| Aprio Technologies http://www.aprio.com/ |
Halo-iOPC, incremental OPC. |
| Blaze DFM http://www.blaze-dfm.com |
Blaze MO, which performs power and timing optimization of a finished design just prior to the handoff to manufacturing. |
| Brion Technologies http://www.brion.com/ |
Tachyon, a hardware-accelerated, image-based data and lithography simulation engine for full-chip RET. |
| Clear Shape Technologies http://www.clearshape.com/ |
Model-based DRC tool. |
| Extreme DA http://www.extreme-da.com/ |
EDA design tools for modeling IC variations and analyzing the statistical impact on extraction, timing, noise, and power to facilitate parametric yield measurement and optimization, |
| Nannor Technologies http://www.nannor.com |
Acuma, a post routing optimization tool that implements recommended design rules for manufacture closure and that optimizes layout for yield improvement. |
| Ponté Solutions http://www.pontesolutions.com/ |
Yield modeling and yield analysis. |
| Predictions Software http://www.icyield.com/ |
EYES, a tool for making integrated circuit yield predictions; PEYE-CAA, which provides the ability to generate and display critical areas of an IC layout; PEYE, a layout modification/analysis tool for the automation of yield and reliability enhancement. |
| Pyxis Technology http://www.pyxistech.com/ |
SOC routing software for sub-100-nm processes that targets yield, lithography, and manufacturability at the design phase. |
| Sagantec http://www.sagantec.com/ |
SiFix, which detects and corrects physical violations in technology and reliability design rules; XTREME, which re-engineers chip interconnect wires to reduce coupling capacitance, crosstalk, and critical net loads to enhance signal integrity, reliability, and yield; and DFM-Fix, a tool that automatically optimizes design tape-out data to eliminate lithography related hot spots. |
| Sigma-C http://www.sigma-c.com/ |
Solid+ microlithography simulator for design and OPC. |
| Silicon Design Systems http://www.silicon-value.com |
K-Route placement-independent interconnect synthesis, which simultaneously uses routing, extraction, analysis and optimization engines. |
| Stratosphere Solutions http://www.stratosol.com |
StratoPro, IP that supports DFM and DFY through process characterization. |
| Virage Logic http://www.viragelogic.com |
FirstPass-Silicon Characterization Lab, which helps ensure reliable IP across a range of foundries. |
| XYALIS http://www.xyalis.com/ |
Software targeting design for manufacturing and mask preparation. |
