ITC to address expanding test role
Rick Nelson, Chief Editor -- Test & Measurement World, 7/18/2006 4:44:00 AM
"Getting More out of Test" is the theme of this year's International Test Conference, to be held October 24-26 in Santa Clara, CA. Program chair Anne Gattiker spoke with chief editor Rick Nelson about why test must involve much more than just separating good parts from bad parts. Gattiker, research staff member at the IBM Austin Research Lab, said attendees will study delay test, compression, defect-based test, analog/mixed signal test, diagnosis, test-data collection, test power, board and system test, and other topics that will help them deal with increasing complexity and process variability.
Nelson: Why is ITC moving to Santa Clara from Austin last year and the East Coast the years before?
Gattiker: We definitely want to move toward our attendee base, and we expect to get a healthy increase in the number of attendees and exhibitors.
Nelson: So from your perspective, the center of gravity is Silicon Valley?
Gattiker: That's true, although without question there is an increase in globalization at the conference. I saw a lot more submissions that were from overseas--with no domestic coauthors--and that’s an exciting change.
Nelson: This year's theme is "Getting More out of Test." Could you elaborate? Why is that theme appropriate for this year?
Gattiker: The theme is purposely broad--"getting more out of test" can involve cost and quality, but the intention is to emphasize the expanding role of test driven by some of the current trends in the industry. It's becoming more and more important for test not to just separate good chips from bad chips or good boards from bad boards but to provide feedback to the fabrication process to help improve manufacturing yields, speed yield-learning ramp-up, and improve debug and time to market.
Nelson: Can you comment on the keynoter and invited speaker and how they will address the theme?
Gattiker: This year we will have one keynote speech and three invited addresses--that's something new for us that we are pretty excited about. At this point the exact topics haven't be determined. The keynote address by Chris Malachowsky, NVIDIA co-founder, fellow, and senior VP of engineering and operations will be part of the plenary session, as it has been in the past.
But the invited addresses will be spread out over three days--one per day, right after lunch, and they will take place in the exhibit hall. The presenters are Gregg Jordan, senior director of manufacturing test engineering at Cisco Systems; Siva Yerramilli, GM for design and technology solutions for the technology and manufacturing group at Intel; and W. Robert Daasch, professor of electrical and computer engineering at Portland State University.Nelson: I understand ITC adding a managers' track and analysts' panel this year.
Gattiker: Yes, on Tuesday, the first day of the conference, we have added considerable content in terms of papers, talks, and panels that emphasize economics, processes, and how to make good decisions about test—all items of great interest to managers. Also on Tuesday we have an executive test panel titled "The Cost of Quality," which will be moderated by Dan Hutcheson [of VLSI Research]. The panelists will be five key executives from IBM, Dell, Cisco Systems, STMicroelectronics, and AMD.
Nelson: You are also adding an analysts' session, I understand.
Gattiker: Yes, we are planning a one and half hour panel titled "A Changing Test Industry: The Analysts’ Perspective." Panelists will include representatives of organizations like VLSI Research and Lehman Brothers. We believe the panel will be of particular interest to people who manage test.
Nelson: Can you comment the workshops?
Gattiker: We have some nice topical workshops--one on silicon debug and diagnosis and one on DFM and DFY, both of which are closely aligned with the theme. We also have a third workshop, on defect-based test.
Nelson: Could you describe defect-based test in 20 words or less?
Gattiker: The definition I like is this one: Instead of asking, "does that work?" as you would in a functional test, you start by asking, "what could go wrong here?" Then you develop test strategies to look for things that could go wrong.
Nelson: Whose responsibility is it to get more out of test--test vendors or test engineers?
Gattiker: I definitely think it's both--the test vendors have a very important role to play. On the ATE side, data collection right now is really quite cumbersome, and ATE needs to adapt to move into its role as a data-collection engine. On the EDA side, vendors have a lot to do, too, including enhancing defect-localization and diagnosis software and taking layout information and making it available for diagnosis. EDA vendors are the ones who probably have the best opportunity to integrate design and test.
Nelson: I recall a panel last year or the year before about data trapped inside a tester…
Gattiker: That's right, the panel on the hermetically sealed tester. ["Dude! Where’s My Data?--Cracking Open the Hermetically Sealed Tester,” Proceedings, International Test Conference 2004.]
Nelson: It will be interesting to see if progress has been made in that area--is a panel of that nature going to be repeated?
Gattiker: Not exactly, but two panels will address the topic--one covers the role of test in yield learning for 65 nm and beyond. This cross-industry panel will examine the range of issues that have an impact on test and yield learning. Another one that’s related is on multicore SOC debug. This panel will examine whether reusable cores have adequate debug features.
Nelson: Is the panel scheduling this year similar to previous years?
Gattiker: We are having fewer panels this year--we are having just one, Wednesday afternoon, panel slot with five panels. There are no more evening panels, but we will hold the wine-and-cheese event after the Wednesday panel session. We really redid the layout this year, but that was one thing we couldn't lose.
We are also holding a special panel on Monday night called "Test Q&A: Behind Closed Doors with Test Experts." The panelists will be challenged to provide opinions on various topical questions in test. We had a similar event last year, and it went over really well.
Nelson: Why the format changes?
Gattiker: We were interested in appealing to the new potential attendees--especially the Bay Area folks--and so we wanted to start later the first day, to encourage people to come, and to wrap up earlier.
Nelson: OK, because many are going to be commuting instead of staying at a nearby hotel…
Gattiker: Exactly right, and so the welcome reception is going to be at the end of Tuesday’s sessions, instead of the Monday before. And then we also wanted make sure we keep our attendees, and that’s why we are having the invited talks each day.
Nelson: Scott Davidson [2005 general vice chair and 2006 general chair] said last year that the challenge in moving to the Bay Area would be to keep everyone from going back to work.
Gattiker: Exactly. We have great content throughout the program, so we put the invited talks after lunch to encourage everyone to stay well into the afternoon each day.
Nelson: What are some of the key topics to be addressed this year?
Gattiker: We have a lot of topics related to the theme--at least four sessions will address diagnosis and debug. We also have a lecture series on design-for-manufacturing and design-for-yield. Other key topics include compression, delay test, and test power. We also have some very nice papers on microprocessors--an area always of interest--and on design for test.
Nelson: Last year's theme was "Survival of the Fittest"--which addressed in part the evolution of ATE from high-cost to relatively low-cost systems. Will low-cost ATE be up to the task of getting more out of test, or will we see a move back to more expensive ATE?
Gattiker: I think we won't need to see the return to expensive test equipment. Actually, getting more out of test is friendly to low-cost structural testers. The key is really going to be getting test data off the chip, which I don't believe needs to be a very expensive operation. Another trend we see is that more and more tests, including timing tests--are moving on chip, which reduces the need for high-cost, high-function test equipment.
Nelson: "Testing from Fab to Field" was the theme in 2004, which Scott Davidson proposed to address what he saw as an unfortunate lack of communication among chip, board, and system engineers. Is the "getting more out of test" theme something that can be addressed at all these levels?
Gattiker: Very much so, especially with the expanding DFM and yield-improvement role. Only at test does the rubber meet the road. At the fab you can run test chips, but you can't be sure you're going to hit all the process corners. When you do a real test of your real product--that represents the first look you get with no modeling and no effort to be representative--it's the real thing. And then I think that extends to board and system test because of potential problems correlating chip and system test. Final-product test gives you the best fidelity in terms of whether a product meets its specs, and it's important to have diagnosis and debug tools at the system-test level.
Nelson: Is the board and system track returning this year?
Gattiker: For four years board and system test has been guaranteed its own track, with a session in each time slot. We have discontinued this special dispensation, but [the board and system track proponents] have, on their own merits, come up with a very nice program anyway.
Nelson: That demonstrates that the effort to emphasize board and system test over past four years was successful.
Gattiker: I think so, yes. They really did very well.
Nelson: Why are DFM, DFY, and yield learning becoming so important?
Gattiker: I think there are two reasons. First is that technology has become so complex that we now have design and process interactions. We experience more systematic defects instead of random defects and there's so much pattern dependence and neighborhood dependence that it's almost impossible to get all the models right and all the test structures right the first time. So you really have to learn based on product test.
And second is the need to deal with aggressive design that handles variability. It used to be that people would do worst-case design. Designers would guarantee that their chips would work at all of the worst-case corners. But with increasing variability they just can't afford to do that anymore. So instead of trying to guarantee that 100% of their chips will work, they play a nasty trick on us [test engineers] and only guarantee that 90% will work. So it's really important for test engineers to test well and provide the feedback that can help determine what's wrong with the process.
Nelson: And how can test engineers learn to do that?
Gattiker: Attend this year's ITC--it will be the best one ever.
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