ITC tutorials span DFT basics to RF test
Rick Nelson, Chief Editor -- Test & Measurement World, 9/21/2006 10:09:00 AM
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The 2006 International Test Conference is scheduled for the week of October 22 in Santa Clara, CA. For more on this year’s ITC, read our interview with program chair Anne Gattiker. |
ITC program committee member and ARM Fellow Rob Aitken, who heads up the pre-conference tutorial effort as well as the lecture series that accompanies the technical program, spoke with chief editor Rick Nelson about the educational offerings planned for this year's Test Week.
Q: Why offer tutorials at ITC? Don’t the attendees already know the basics of test?
A: If you look at the demographics, you’ll find that typically about 45% of the attendees at ITC are there for the first time. By offering the Sunday and Monday tutorials as well as the lecture series [with lectures interspersed throughout the ITC technical program] we can accommodate attendees who know a lot about test or very little about it. And the tutorials themselves are mixed—some are very introductory, answering questions like, "What’s DFT all about?". Others are much more focused on advanced topics such as DFT for RF circuitry.
Q: Are educational credits awarded for participation in the tutorials?
A: Yes. The TTTC [the IEEE Computer Society Test Technology Technical Council] awards four units for participation in each full-day tutorial. On completion of 16 units, attendees receive an IEEE TTTC Test Technology Certificate. The tutorials accompanying ITC represent about half the educational programs the TTTC offers during the year.
Q: I see from the advance program that one new tutorial for this year is titled "Semiconductor Test and DFT Fundamentals." Is this one offered in response to popular demand?
A: Very much so. A couple of years ago, we offered a one-and-a-half hour class on the topic that was very popular, and this full-day tutorial is an extension of that—what is this test thing all about and how can I learn more about it?
Q: Another topic is "Design-for-Testability for RF Circuits and Systems"—is this driven by new DFT capabilities in the RF realm?
A: Yes, but it’s driven also by new needs. With wireless business booming, many circuit designers and test people who haven’t been exposed to RF test fundamentals are going to have to know something about them. This particular tutorial [presented by Martin Margala of the University of Rochester and Sule Ozev of Duke University] will discuss how to take advantage of some of the techniques that have been developed over the years in digital and analog mixed-signal test and apply them to the RF domain.
Q: I notice there is a new tutorial on design-for-manufacturability, presented in part by Yervant Zorian of Virage Logic. DFM until now has been more the domain of the Design Automation Conference. What’s driving the inclusion of this topic at ITC?
A: This is actually the second year that we have addressed DFM, but this year we have a full tutorial dedicated to it. The tutorial ties in nicely with the DFM and yield workshop that Yervant is organizing for Thursday and Friday at the end of the conference [the IEEE International Workshop on Design-for-Manufacturability & Yield 2006]. Until recently, I think people have just assumed that design-for-manufacturability and yield all belong exclusively in the domain of design, but the final arbiter of yield is always test, so the interaction between them has to be understood.
Q: You are offering a new session on memory test called "Memory Test Challenges--A Practical and Implementation View of BIST and other DFT Techniques." Memory BIST has been around for many years. Are there any particular issues driving a special interest in memory test this year?
A: We have offered a tutorial on memory test for many years that provides very useful fundamental knowledge—the algorithms, the mechanics of failure, and the methods of test. What’s new is that DFT engineers who suddenly have to work with 90-nm or 65-nm designs need to put BIST on many memory blocks on every chip. Placing test and repair circuitry on hundreds or thousands of memory blocks is quite complicated. The purpose of the tutorial [presented by Vinay Jayaram and Sherry Lai of Texas Instruments] is to give a practical description of the issues involved, the problems engineers are likely to encounter, and the tools available to help.
Q: You are offering a tutorial on digital timing measurement—is this essentially a debug topic?
A: Yes, and a very practical one, because test engineers are going to spend a lot of their time with oscilloscopes and other instruments trying to debug their devices and their tests The presenter [W. Maichen of Teradyne] has huge amounts of practical knowledge that he can pass on to attendees.
Q: Soft errors are the focus of another new tutorial. So soft errors are increasingly causing problems at 90 nm and 65 nm?
A: Yes, and not just in memories. As we move to 45 nm, soft errors are more likely to appear in flip-flops and standard logic.
Q: You’ve also got a tutorial called "Debugging Compression-based Tests Like EDT, OPMISR, X-DBIST, and LBIST."
A: Yes. If you are using compression and have a failing scan chain, you need to learn how to find out what’s happening despite the scan data’s being compressed. Nikhil Dakwala [of Stridge] will describe how to detect, analyze, locate, fix, and log failures based on compressed data.
Q: Are all the tutorial topics related to semiconductor test?
A: No, we are continuing to offer a tutorial on boundary-scan [Designing Testable Multiboard Systems Using 1149.1 Architectures].
Q: You are offering lectures interspersed with the technical program dealing with some of the same topics—like DFM. What’s the goal of the lecture series?
A: The lectures are mini embedded tutorials that give attendees a quick overview of a subject so they can speak intelligently to exhibitors and understand the technical papers. We have put a lot of effort into ensuring that the lectures don’t conflict with related technical presentations. While the tutorials can approach the equivalent of a graduate-level course in some instances, the lectures are for people who can’t afford to spend eight hours at a full-day tutorial but who need information they can take home from the conference and put to work the next Monday.
Q: I notice that you are the coordinator of a lecture series called "Test Experiments and Case Studies." What’s the goal of that one?
For example, look at the interesting test data Peter Maxwell [of Avago Technologies] has been publishing over the last 20 years. Lots of other people would like to collect similar data, but they need to know how to conduct their own experiments. Our thinking is that by giving people essentially the Science 101 about how to conduct a test experiment, we’ll have more and better trained experimenters conducting more and better experiments and publishing the results at ITC, so the whole community wins.
For more on this year’s International Test Conference, read our interview with program chair Anne Gattiker.
