Accellera issues revised VHDL standard
-- Test & Measurement World, 10/12/2006 7:09:00 AM
A new revision to Accellera’s VHDL standard integrates the Property Specification Language (PSL), adds intellectual property (IP) protection methods, and offers improvements that increase designer productivity, including the implementation of a hierarchical signal reference to allow test benches to drive and read signals deep in a design.
The revision was approved by the members and board of directors of Accellera, the electronics industry organization focused on electronic design automation standards.
In July, the organization announced approval of the VHDL Applications Programming Interface (API) standard known as VHPI. Both standards have been transferred to the IEEE for their consideration as revisions to the VHDL standard, IEEE 1076-2002. Accellera's VHDL Technical Subcommittee (TSC) works with the IEEE VHDL Analysis and Standardization Group (VASG) on standardization.
"Accellera has well-established processes for delivering standards in a timely manner and transferring them to the IEEE," said Shrenik Mehta, chair of Accellera. "For VHDL, the IEEE granted us the permission to revise the language, and with the efforts of over 50 engineers representing more than 20 companies, we were able to finalize the development and approve a revised specification in less than a year."
"This revision has truly been a tag-team effort," said Jim Lewis, IEEE VASG chair.
"The IEEE VASG started the work in early 2003, and Accellera's VHDL Technical Subcommittee took over the work in 2005, funded its technical editing, and did super-human work to finalize it. We are pleased that these language extensions and productivity enhancements are standardized for industry adoption."
"Accellera's efforts to enhance VHDL will continue," added Lance Thompson, Accellera's VHDL TSC Chair, "We encourage individuals and companies to join the VHDL Technical Subcommittee and Accellera to help further our work."
The Accellera-approved VHDL standard integrates PSL, allowing PSL statements to appear in the body of VHDL description. In addition, design units were created that permit PSL files to be separate from the design. The standard adds IP protection mechanisms and supports methods that allow designers to specify what portions of the design are to be encrypted and protected, what method to employ, and the name of the key to use for decryption. Further, the standard adds facilities to make objects (usually signals) visible from within an encrypted and protected region.
