ITC: Validation and test synergy
-- Test & Measurement World, 10/30/2006 10:20:00 AM
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Siva Yerramilli, GM of Design and Technology Solutions at Intel, addressed validation and test synergy during his Wednesday ITC presentation. Moore’s Law is alive and well, he said, but because of challenges due to design complexity, process variation, and power and thermal management, “there are no free lunches.”
Many of these effects are expensive or impossible to design out and need to be validated on silicon, he said. Design, he added, does not account for many parameters, and design for worst-case margins and the establishment of adequate worst-case guard-banding can lead to unacceptable power performance. Further, he said, adaptive power-management techniques such as dynamic voltage scaling cannot be fully validated pre-silicon.
Therefore, post-silicon validation has become increasingly important to qualify products. “System-level validation is absolutely necessary and will always be needed.” Unfortunately, he added, system-level validation has no coverage metric and requires long test sequences, ATE tests often provide inadequate coverage, and system-level debug to find root causes of failures to generate ECOs is expensive.
Consequently, Yerramilli said, rising silicon validation costs are predominately due to increasing reliance on system-level validation. These costs could be addressed, he said, by leveraging designers’ intelligence in creating directed, targeted tests, with pre-silicon validation linked to post-silicon validation and manufacturing test processes.
Unfortunately, he said, pre-silicon and post-silicon validation linkages are virtually nonexistent. Pre-silicon and post-silicon validation engineers belong to different groups, he said, with post-silicon teams focusing on system-level ATE tests. Why, he asked, are there such barriers between the groups, and can they be broken?
Both domains, he said, need test generation, both domains need architectural and micro-architectural knowledge, and both domains need a coverage metric, and there should be a significant opportunity to share methods and tools. “Validation and test can benefit from leveraging their respective strengths,” he said.
He urged the adoption of structured design for validation processes early on in the design process, instead of adding them as an afterthought. In addition, he said, improvements in manufacturing test processes can help establish a tight feedback loop so designers can learn from manufacturing test.
But addressing post-silicon validation early in the design phase is a challenge requiring innovation in terms of developing high-level models and model-based test-generation processes, Yerramilli said, concluding that innovation is necessary to exploit test and validation synergy. He issued a call to action that the test and validation communities work together to share technologies and methods across the two domains to bring mutual benefits with respect to productivity and efficiency.
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