Guest commentary: 65-nm IC designs need DWT as well as DFM

Sanjiv Taneja, Cadence Design Systems -- Test & Measurement World, 2/6/2007 3:54:00 AM

As process geometries shrink to 65 nm and below, manufacturing test must expand its role in the design, implementation, and production of semiconductor devices. Much like DFM and its manufacturing-driven design flow—which is an accepted requirement today—a “test-driven” design and implementation flow is now at the forefront of chip-design concerns.

Here are the key drivers mandating this change:

• the need for delay test to ensure product quality,
• the requirement for on-chip test-data compression to reduce the cost of test,
• the significant growth in the use of on-chip memory blocks,
• the wide adoption of low-power design flows,
• the increased power consumption during test, and
• dynamic defect behavior caused by advanced physics effects in nanometer technologies.

These factors contribute to a highly complex interaction among test and the design and implementation flows. As this emerging role for test is broader than traditional design for test (DFT), I refer to it as “design with test” (DWT).

A DWT methodology encompasses timing-aware, power-aware, and physically aware test addressing nanometer test challenges. It does this through a “deep integration” among design, test, and implementation flows performing a global optimization across multiple constraints such as timing, area, power, yield, and test. The “deep integration” enables complex interactions among synthesis, test, floor planning, and placement and routing to be modeled accurately, while the global optimization approach generates high-quality silicon. The key elements of the DWT methodology are best illustrated in the following examples.

In nanometer processes, delay tests using timing-aware automatic test pattern generation (ATPG) engines are required to detect advanced delay defects such as resistive shorts and resistive opens.  However, timing-aware ATPG requires significant accuracy from a deep level of integration between test, physical design, and timing analysis. Recent empirical studies using a statistical quality defect model—proposed by the Japanese consortia STARC (Semiconductor Technology and Research Consortia) and presented at the 2005 International Test Conference—demonstrated conclusively that transition tests based on actual circuit timings detect a greater number of small delay defects. The result is up to 40% improvement in the DPM (defects per million) metric. This means semiconductor providers can meet their stringent quality and cost requirements, which are hard to meet without the “test/timing analysis” integration embodied in the DWT methodology.

Much like test-pattern generation, physically-aware test insertion of test structures—such as scan chains, boundary scan, memory built-in self-test (BIST), compression, on-product clock generation, and IEEE 1500 core test—must be tied closely with the implementation flow. On-chip test compression in particular has a significant bearing on timing closure. The insertion of on-chip compression logic to manage test cost results in a small number of large scan chains being fragmented into a large number of small scan chains. This explosion in the number of scan chains creates routing congestion and places additional challenges on scan chain reordering and the specific placement of compression and decompression logic structures, thereby impacting the overall quality of silicon results. To alleviate these challenges, physically aware test takes physical constraints into account—enabled by the “deep integration” of the DWT methodology—and fully realizes the cost benefits of compression.

With the growing concern over power consumption in the test mode, the interplay of test with the implementation flow takes on special significance. Excessive power consumption in the test mode can result in false fails or even destruction of the device under test.  A DWT methodology supporting power-aware test ensures “power optimized” test patterns by taking switching activity consideration into account while recognizing the power management techniques incorporated in the device by the designer.

To keep production costs down and ensure that tests run first time on the tester, a DWT methodology provides a robust verification and simulation of the test features prior to chip tapeout. It enables the test features to be validated with the same rigor as non-test functional features using technologies such as equivalence checking, constraint generation, and advanced analysis.

The quality, cost, and yield challenges in nanometer test represent a unique opportunity for the EDA industry to provide higher value. A DWT methodology enabled by a tight integration of test in the design and implementation flow is a great way for the EDA industry to become a trusted advisor and partner to its customers.

Sanjiv Taneja is VP of R&D for Cadence Design Systems' Encounter Test division.